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/linux-6.12.1/arch/arm/boot/dts/marvell/
Dkirkwood-t5325.dts23 reg = <0x00000000 0x20000000>;
33 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
76 flash@0 {
81 reg = <0>;
82 mode = <0>;
84 partition@0 {
85 reg = <0x0 0x80000>;
90 reg = <0x80000 0x40000>;
95 reg = <0xc0000 0x10000>;
100 reg = <0xd0000 0x10000>;
[all …]
Darmada-370-xp.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/cfg/
Dbz.c19 #define IWL_BZ_NVM_VERSION 0x0a1d
22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET 0x880000
25 #define IWL_BZ_DCCM2_LEN 0x8000
26 #define IWL_BZ_SMEM_OFFSET 0x400000
27 #define IWL_BZ_SMEM_LEN 0xD0000
82 .mac_addr_from_csr = 0x30, \
88 .min_umac_error_event_table = 0xD0000, \
89 .d3_debug_data_base_addr = 0x401000, \
[all …]
Dsc.c19 #define IWL_SC_NVM_VERSION 0x0a1d
22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_SC_DCCM2_OFFSET 0x880000
25 #define IWL_SC_DCCM2_LEN 0x8000
26 #define IWL_SC_SMEM_OFFSET 0x400000
27 #define IWL_SC_SMEM_LEN 0xD0000
91 .mac_addr_from_csr = 0x30, \
97 .min_umac_error_event_table = 0xD0000, \
98 .d3_debug_data_base_addr = 0x401000, \
[all …]
Dax210.c19 #define IWL_AX210_NVM_VERSION 0x0a1d
22 #define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_AX210_DCCM2_OFFSET 0x880000
25 #define IWL_AX210_DCCM2_LEN 0x8000
26 #define IWL_AX210_SMEM_OFFSET 0x400000
27 #define IWL_AX210_SMEM_LEN 0xD0000
96 .mac_addr_from_csr = 0x380, \
103 .min_umac_error_event_table = 0x400000, \
104 .d3_debug_data_base_addr = 0x401000, \
[all …]
D22000.c19 #define IWL_22000_NVM_VERSION 0x0a1d
22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_22000_DCCM2_OFFSET 0x880000
25 #define IWL_22000_DCCM2_LEN 0x8000
26 #define IWL_22000_SMEM_OFFSET 0x400000
27 #define IWL_22000_SMEM_LEN 0xD0000
84 .mac_addr_from_csr = 0x380, \
91 .min_umac_error_event_table = 0x400000, \
92 .d3_debug_data_base_addr = 0x401000, \
[all …]
/linux-6.12.1/drivers/staging/media/atomisp/pci/
Dstr2mem_defs.h19 #define _STR2MEM_CRUN_BIT 0x100000
20 #define _STR2MEM_CMD_BITS 0x0F0000
21 #define _STR2MEM_COUNT_BITS 0x00FFFF
23 #define _STR2MEM_BLOCKS_CMD 0xA0000
24 #define _STR2MEM_PACKETS_CMD 0xB0000
25 #define _STR2MEM_BYTES_CMD 0xC0000
26 #define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
28 #define _STR2MEM_SOFT_RESET_REG_ID 0
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: flash@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/dove/
Dpmu.txt24 - #power-domain-cells: must be 0.
35 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
43 #power-domain-cells = <0>;
44 marvell,pmu_pwr_mask = <0x00000008>;
45 marvell,pmu_iso_mask = <0x00000001>;
50 #power-domain-cells = <0>;
51 marvell,pmu_pwr_mask = <0x00000004>;
52 marvell,pmu_iso_mask = <0x00000002>;
/linux-6.12.1/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/linux-6.12.1/Documentation/sound/cards/
Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/linux-6.12.1/arch/arm/mach-dove/
Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dmarvell,nand-controller.yaml66 minimum: 0
71 - minimum: 0
156 reg = <0xd0000 0x54>;
158 #size-cells = <0>;
160 clocks = <&coredivclk 0>;
162 nand@0 {
163 reg = <0>;
165 nand-rb = <0>;
177 partition@0 {
179 reg = <0x00000000 0x40000000>;
[all …]
/linux-6.12.1/Documentation/networking/
Dgeneric-hdlc.rst140 insmod n2 hw=0x300,10,0xD0000,01
148 insmod c101 hw=9,0xdc000
/linux-6.12.1/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/linux-6.12.1/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h19 #define SUN8I_MIXER_GLOBAL_CTL 0x0
20 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
21 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
22 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
24 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
26 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
28 #define DE2_MIXER_UNIT_SIZE 0x6000
29 #define DE3_MIXER_UNIT_SIZE 0x3000
31 #define DE2_BLD_BASE 0x1000
32 #define DE2_CH_BASE 0x2000
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7-mba7.dtsi27 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
43 button-0 {
86 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
87 <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
226 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
227 cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
234 pinctrl-0 = <&pinctrl_ecspi2>;
240 pinctrl-0 = <&pinctrl_enet1>;
249 #size-cells = <0>;
251 ethphy1_0: ethernet-phy@0 {
[all …]
Dimx6q-ba16.dtsi51 reg = <0x10000000 0x40000000>;
57 pinctrl-0 = <&pinctrl_display>;
58 pwms = <&pwm1 0 5000000 0>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
86 enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
127 pinctrl-0 = <&pinctrl_usbotg_vbus>;
135 pinctrl-0 = <&pinctrl_audmux>;
142 pinctrl-0 = <&pinctrl_ecspi1>;
145 flash: flash@0 {
150 reg = <0>;
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/sn0/
Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/linux-6.12.1/sound/isa/msnd/
Dmsnd_pinnacle.c95 snd_msnd_DAPQ(chip, 0); in snd_msnd_eval_dsp_msg()
100 chip->playDMAPos = 0; in snd_msnd_eval_dsp_msg()
111 chip->captureDMAPos = 0; in snd_msnd_eval_dsp_msg()
139 ": DSP message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
151 dev_dbg(chip->card->dev, LOGNAME ": HIMT message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
175 head = 0; in snd_msnd_interrupt()
198 while (timeout-- > 0) { in snd_msnd_reset_dsp()
200 return 0; in snd_msnd_reset_dsp()
223 if (snd_msnd_reset_dsp(chip, &info) < 0) { in snd_msnd_probe()
232 "I/O 0x%lx-0x%lx, IRQ %d, memory mapped to 0x%lX-0x%lX\n", in snd_msnd_probe()
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
/linux-6.12.1/drivers/soc/dove/
Dpmu.c22 #define PMC_SW_RST 0x30
23 #define PMC_IRQ_CAUSE 0x50
24 #define PMC_IRQ_MASK 0x54
26 #define PMU_PWR 0x10
27 #define PMU_ISO 0x58
60 return 0; in pmu_reset_reset()
74 return 0; in pmu_reset_assert()
88 return 0; in pmu_reset_deassert()
174 return 0; in pmu_domain_power_off()
208 return 0; in pmu_domain_power_on()
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dmme_regs.h22 #define mmMME_ARCH_STATUS 0xD0000
24 #define mmMME_ARCH_A_BASE_ADDR_HIGH 0xD0008
26 #define mmMME_ARCH_B_BASE_ADDR_HIGH 0xD000C
28 #define mmMME_ARCH_CIN_BASE_ADDR_HIGH 0xD0010
30 #define mmMME_ARCH_COUT_BASE_ADDR_HIGH 0xD0014
32 #define mmMME_ARCH_BIAS_BASE_ADDR_HIGH 0xD0018
34 #define mmMME_ARCH_A_BASE_ADDR_LOW 0xD001C
36 #define mmMME_ARCH_B_BASE_ADDR_LOW 0xD0020
38 #define mmMME_ARCH_CIN_BASE_ADDR_LOW 0xD0024
40 #define mmMME_ARCH_COUT_BASE_ADDR_LOW 0xD0028
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/net/wireless/microchip/wilc1000/
Dwlan.h22 #define WORD_ALIGNMENT_PAD 0
47 #define WILC_PERIPH_REG_BASE 0x1000
48 #define WILC_CHANGING_VIR_IF 0x108c
50 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
51 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
52 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
53 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
54 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
55 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
56 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
[all …]

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