Lines Matching +full:0 +full:xd0000
22 #define WORD_ALIGNMENT_PAD 0
47 #define WILC_PERIPH_REG_BASE 0x1000
48 #define WILC_CHANGING_VIR_IF 0x108c
50 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
51 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
52 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
53 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
54 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
55 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
56 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
57 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
58 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
59 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
63 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
64 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
65 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
66 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
68 #define WILC_RF_REVISION_ID 0x13f4
71 #define WILC_VMM_TX_TBL_BASE 0x150400
72 #define WILC_VMM_RX_TBL_BASE 0x150500
74 #define WILC_VMM_BASE 0x150000
76 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
77 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
78 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
79 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
80 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
82 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
84 #define WILC_SPI_REG_BASE 0xe800
86 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
87 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
88 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
89 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
90 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
91 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
92 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
93 #define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
94 #define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
96 #define WILC_SPI_WAKEUP_REG 0x1
99 #define WILC_SPI_CLK_STATUS_REG 0x0f
101 #define WILC_SPI_HOST_TO_FW_REG 0x0b
102 #define WILC_SPI_HOST_TO_FW_BIT BIT(0)
104 #define WILC_SPI_FW_TO_HOST_REG 0x10
105 #define WILC_SPI_FW_TO_HOST_BIT BIT(0)
110 #define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30
116 #define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
123 #define WILC_SDIO_WAKEUP_REG 0xf0
124 #define WILC_SDIO_WAKEUP_BIT BIT(0)
126 #define WILC_SDIO_CLK_STATUS_REG 0xf1
127 #define WILC_SDIO_CLK_STATUS_BIT BIT(0)
129 #define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
131 #define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
132 #define WILC_SDIO_IRQ_FLAG_REG 0xf7
133 #define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
135 #define WILC_SDIO_HOST_TO_FW_REG 0xfa
136 #define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
138 #define WILC_SDIO_FW_TO_HOST_REG 0xfc
139 #define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
142 #define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
143 #define WILC_SDIO_FBR_DATA_REG 0x10F
145 #define WILC_SDIO_F1_DATA_REG 0x0
146 #define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
148 #define WILC_AHB_DATA_MEM_BASE 0x30000
149 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
154 #define WILC_FW_HOST_COMM 0x13c0
155 #define WILC_GP_REG_0 0x149c
156 #define WILC_GP_REG_1 0x14a0
158 #define GLOBAL_MODE_CONTROL 0x1614
159 #define PWR_SEQ_MISC_CTRL 0x3008
161 #define WILC_GLOBAL_MODE_ENABLE_WIFI BIT(0)
164 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
174 #define WILC_CORTUS_INTERRUPT_BASE 0x10A8
175 #define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4)
176 #define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8)
179 #define WILC_REG_4_TO_1_RX 0x1e1c
182 #define WILC_REG_4_TO_1_TX_BANK0 0x1e9c
184 #define WILC_CORTUS_RESET_MUX_SEL 0x1118
185 #define WILC_CORTUS_BOOT_REGISTER 0xc0000
187 #define WILC_CORTUS_BOOT_FROM_IRAM 0x71
189 #define WILC_1000_BASE_ID 0x100000
191 #define WILC_1000_BASE_ID_2A 0x1002A0
194 #define WILC_1000_BASE_ID_2B 0x1002B0
198 #define WILC_CHIP_REV_FIELD GENMASK(11, 0)
206 #define WILC_NET_PKT 0
210 #define WILC_CFG_QUERY 0
236 #define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)
238 #define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)
240 #define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)
245 #define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)
255 /* 15:0 = DMA count in words. */
264 #define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
278 /* 0: Clear INT0 */
288 #define CLR_INT0 BIT(0)
310 #define IS_MANAGMEMENT 0x100
311 #define IS_MANAGMEMENT_CALLBACK 0x080
312 #define IS_MGMT_STATUS_SUCCES 0x040
313 #define IS_MGMT_AUTH_PKT 0x010
323 AC_VO_Q = 0,