22 #define PMC_SW_RST		0x30
23 #define PMC_IRQ_CAUSE		0x50
24 #define PMC_IRQ_MASK		0x54
26 #define PMU_PWR			0x10
27 #define PMU_ISO			0x58
60 	return 0;  in pmu_reset_reset()
74 	return 0;  in pmu_reset_assert()
88 	return 0;  in pmu_reset_deassert()
174 	return 0;  in pmu_domain_power_off()
208 	return 0;  in pmu_domain_power_on()
233 	u32 done = ~0;  in pmu_irq_handler()
235 	if (stat == 0) {  in pmu_irq_handler()
274 	writel(0, pmu->pmc_base + PMC_IRQ_MASK);  in dove_init_pmu_irq()
275 	writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);  in dove_init_pmu_irq()
286 					     IRQ_NOREQUEST | IRQ_NOPROBE, 0,  in dove_init_pmu_irq()
294 	gc = irq_get_domain_generic_chip(domain, 0);  in dove_init_pmu_irq()
296 	gc->chip_types[0].regs.mask = PMC_IRQ_MASK;  in dove_init_pmu_irq()
297 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;  in dove_init_pmu_irq()
298 	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;  in dove_init_pmu_irq()
306 	return 0;  in dove_init_pmu_irq()
347 					  0, NR_PMU_IRQS);  in dove_init_pmu_legacy()
349 	return 0;  in dove_init_pmu_legacy()
355  *	reg = <0xd0000 0x8000> <0xd8000 0x8000>;
360  *		#power-domain-cells = <0>;
361  *		marvell,pmu_pwr_mask = <0x00000008>;
362  *		marvell,pmu_iso_mask = <0x00000001>;
366  *		#power-domain-cells = <0>;
367  *		marvell,pmu_pwr_mask = <0x00000004>;
368  *		marvell,pmu_iso_mask = <0x00000002>;
382 		return 0;  in dove_init_pmu()
387 		return 0;  in dove_init_pmu()
396 	pmu->pmc_base = of_iomap(pmu->of_node, 0);  in dove_init_pmu()
437 						 0, &args);  in dove_init_pmu()
438 		if (ret == 0) {  in dove_init_pmu()
440 				domain->rst_mask = BIT(args.args[0]);  in dove_init_pmu()
448 	parent_irq = irq_of_parse_and_map(pmu->of_node, 0);  in dove_init_pmu()
457 	return 0;  in dove_init_pmu()