1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2024 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_SC_UCODE_API_MAX 93 14 15 /* Lowest firmware API version supported */ 16 #define IWL_SC_UCODE_API_MIN 90 17 18 /* NVM versions */ 19 #define IWL_SC_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_SC_DCCM2_OFFSET 0x880000 25 #define IWL_SC_DCCM2_LEN 0x8000 26 #define IWL_SC_SMEM_OFFSET 0x400000 27 #define IWL_SC_SMEM_LEN 0xD0000 28 29 #define IWL_SC_A_FM_B_FW_PRE "iwlwifi-sc-a0-fm-b0" 30 #define IWL_SC_A_FM_C_FW_PRE "iwlwifi-sc-a0-fm-c0" 31 #define IWL_SC_A_HR_A_FW_PRE "iwlwifi-sc-a0-hr-b0" 32 #define IWL_SC_A_HR_B_FW_PRE "iwlwifi-sc-a0-hr-b0" 33 #define IWL_SC_A_GF_A_FW_PRE "iwlwifi-sc-a0-gf-a0" 34 #define IWL_SC_A_GF4_A_FW_PRE "iwlwifi-sc-a0-gf4-a0" 35 #define IWL_SC_A_WH_A_FW_PRE "iwlwifi-sc-a0-wh-a0" 36 #define IWL_SC2_A_FM_C_FW_PRE "iwlwifi-sc2-a0-fm-c0" 37 #define IWL_SC2_A_WH_A_FW_PRE "iwlwifi-sc2-a0-wh-a0" 38 #define IWL_SC2F_A_FM_C_FW_PRE "iwlwifi-sc2f-a0-fm-c0" 39 #define IWL_SC2F_A_WH_A_FW_PRE "iwlwifi-sc2f-a0-wh-a0" 40 41 #define IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(api) \ 42 IWL_SC_A_FM_B_FW_PRE "-" __stringify(api) ".ucode" 43 #define IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(api) \ 44 IWL_SC_A_FM_C_FW_PRE "-" __stringify(api) ".ucode" 45 #define IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(api) \ 46 IWL_SC_A_HR_A_FW_PRE "-" __stringify(api) ".ucode" 47 #define IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(api) \ 48 IWL_SC_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 49 #define IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(api) \ 50 IWL_SC_A_GF_A_FW_PRE "-" __stringify(api) ".ucode" 51 #define IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 52 IWL_SC_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode" 53 #define IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(api) \ 54 IWL_SC_A_WH_A_FW_PRE "-" __stringify(api) ".ucode" 55 #define IWL_SC2_A_FM_C_FW_MODULE_FIRMWARE(api) \ 56 IWL_SC2_A_FM_C_FW_PRE "-" __stringify(api) ".ucode" 57 #define IWL_SC2_A_WH_A_FW_MODULE_FIRMWARE(api) \ 58 IWL_SC2_A_WH_A_FW_PRE "-" __stringify(api) ".ucode" 59 #define IWL_SC2F_A_FM_C_FW_MODULE_FIRMWARE(api) \ 60 IWL_SC2F_A_FM_C_FW_PRE "-" __stringify(api) ".ucode" 61 #define IWL_SC2F_A_WH_A_FW_MODULE_FIRMWARE(api) \ 62 IWL_SC2F_A_WH_A_FW_PRE "-" __stringify(api) ".ucode" 63 64 static const struct iwl_base_params iwl_sc_base_params = { 65 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 66 .num_of_queues = 512, 67 .max_tfd_queue_size = 65536, 68 .shadow_ram_support = true, 69 .led_compensation = 57, 70 .wd_timeout = IWL_LONG_WD_TIMEOUT, 71 .max_event_log_size = 512, 72 .shadow_reg_enable = true, 73 .pcie_l1_allowed = true, 74 }; 75 76 #define IWL_DEVICE_BZ_COMMON \ 77 .ucode_api_max = IWL_SC_UCODE_API_MAX, \ 78 .ucode_api_min = IWL_SC_UCODE_API_MIN, \ 79 .led_mode = IWL_LED_RF_STATE, \ 80 .nvm_hw_section_num = 10, \ 81 .non_shared_ant = ANT_B, \ 82 .dccm_offset = IWL_SC_DCCM_OFFSET, \ 83 .dccm_len = IWL_SC_DCCM_LEN, \ 84 .dccm2_offset = IWL_SC_DCCM2_OFFSET, \ 85 .dccm2_len = IWL_SC_DCCM2_LEN, \ 86 .smem_offset = IWL_SC_SMEM_OFFSET, \ 87 .smem_len = IWL_SC_SMEM_LEN, \ 88 .apmg_not_supported = true, \ 89 .trans.mq_rx_supported = true, \ 90 .vht_mu_mimo_supported = true, \ 91 .mac_addr_from_csr = 0x30, \ 92 .nvm_ver = IWL_SC_NVM_VERSION, \ 93 .trans.rf_id = true, \ 94 .trans.gen2 = true, \ 95 .nvm_type = IWL_NVM_EXT, \ 96 .dbgc_supported = true, \ 97 .min_umac_error_event_table = 0xD0000, \ 98 .d3_debug_data_base_addr = 0x401000, \ 99 .d3_debug_data_length = 60 * 1024, \ 100 .mon_smem_regs = { \ 101 .write_ptr = { \ 102 .addr = LDBG_M2S_BUF_WPTR, \ 103 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 104 }, \ 105 .cycle_cnt = { \ 106 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 107 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 108 }, \ 109 }, \ 110 .trans.umac_prph_offset = 0x300000, \ 111 .trans.device_family = IWL_DEVICE_FAMILY_SC, \ 112 .trans.base_params = &iwl_sc_base_params, \ 113 .min_txq_size = 128, \ 114 .gp2_reg_addr = 0xd02c68, \ 115 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 116 .mon_dram_regs = { \ 117 .write_ptr = { \ 118 .addr = DBGC_CUR_DBGBUF_STATUS, \ 119 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 120 }, \ 121 .cycle_cnt = { \ 122 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 123 .mask = 0xffffffff, \ 124 }, \ 125 .cur_frag = { \ 126 .addr = DBGC_CUR_DBGBUF_STATUS, \ 127 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 128 }, \ 129 }, \ 130 .mon_dbgi_regs = { \ 131 .write_ptr = { \ 132 .addr = DBGI_SRAM_FIFO_POINTERS, \ 133 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 134 }, \ 135 } 136 137 #define IWL_DEVICE_SC \ 138 IWL_DEVICE_BZ_COMMON, \ 139 .uhb_supported = true, \ 140 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 141 .num_rbds = IWL_NUM_RBDS_SC_EHT, \ 142 .ht_params = &iwl_22000_ht_params 143 144 /* 145 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 146 * A-MPDU, with additional overhead to account for processing time. 147 */ 148 #define IWL_NUM_RBDS_SC_EHT (512 * 16) 149 150 const struct iwl_cfg_trans_params iwl_sc_trans_cfg = { 151 .device_family = IWL_DEVICE_FAMILY_SC, 152 .base_params = &iwl_sc_base_params, 153 .mq_rx_supported = true, 154 .rf_id = true, 155 .gen2 = true, 156 .integrated = true, 157 .umac_prph_offset = 0x300000, 158 .xtal_latency = 12000, 159 .low_latency_xtal = true, 160 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 161 }; 162 163 const char iwl_sc_name[] = "Intel(R) TBD Sc device"; 164 165 const struct iwl_cfg iwl_cfg_sc = { 166 .fw_name_mac = "sc", 167 IWL_DEVICE_SC, 168 }; 169 170 const char iwl_sc2_name[] = "Intel(R) TBD Sc2 device"; 171 172 const struct iwl_cfg iwl_cfg_sc2 = { 173 .fw_name_mac = "sc2", 174 IWL_DEVICE_SC, 175 }; 176 177 const char iwl_sc2f_name[] = "Intel(R) TBD Sc2f device"; 178 179 const struct iwl_cfg iwl_cfg_sc2f = { 180 .fw_name_mac = "sc2f", 181 IWL_DEVICE_SC, 182 }; 183 184 MODULE_FIRMWARE(IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 185 MODULE_FIRMWARE(IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 186 MODULE_FIRMWARE(IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 187 MODULE_FIRMWARE(IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 188 MODULE_FIRMWARE(IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 189 MODULE_FIRMWARE(IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 190 MODULE_FIRMWARE(IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 191 MODULE_FIRMWARE(IWL_SC2_A_FM_C_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 192 MODULE_FIRMWARE(IWL_SC2_A_WH_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 193 MODULE_FIRMWARE(IWL_SC2F_A_FM_C_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 194 MODULE_FIRMWARE(IWL_SC2F_A_WH_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 195