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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/linux-6.12.1/arch/arm/boot/dts/aspeed/
Dopenbmc-flash-layout-128.dtsi8 u-boot@0 {
9 reg = <0x0 0xe0000>; // 896KB
14 reg = <0xe0000 0x20000>; // 128KB
19 reg = <0x100000 0x900000>; // 9MB
24 reg = <0xa00000 0x5600000>; // 86MB
29 reg = <0x6000000 0x2000000>; // 32MB
Dopenbmc-flash-layout-64.dtsi11 u-boot@0 {
12 reg = <0x0 0xe0000>; // 896KB
17 reg = <0xe0000 0x20000>; // 128KB
22 reg = <0x100000 0x900000>; // 9MB
27 reg = <0xa00000 0x2000000>; // 32MB
32 reg = <0x2a00000 0x1600000>; // 22MB
Dopenbmc-flash-layout-64-alt.dtsi11 u-boot@0 {
12 reg = <0x0 0xe0000>; // 896KB
17 reg = <0xe0000 0x20000>; // 128KB
22 reg = <0x100000 0x900000>; // 9MB
27 reg = <0xa00000 0x2000000>; // 32MB
32 reg = <0x2a00000 0x1600000>; // 22MB
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-mdm9607.yaml38 reg = <0x900000 0x4000>;
Dqcom,gcc-mdm9615.yaml44 reg = <0x900000 0x4000>;
Dqcom,gcc-msm8660.yaml49 reg = <0x900000 0x4000>;
/linux-6.12.1/arch/arm/include/uapi/asm/
Dunistd.h17 #define __NR_OABI_SYSCALL_BASE 0x900000
18 #define __NR_SYSCALL_MASK 0x0fffff
21 #define __NR_SYSCALL_BASE 0
33 #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000)
/linux-6.12.1/arch/arm/boot/dts/gemini/
Dgemini-ssi1328.dts17 memory@0 {
20 reg = <0x00000000 0x8000000>;
28 bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M";
37 #size-cells = <0>;
54 ethernet-port@0 {
67 reg = <0x30000000 0x03200000>;
70 pinctrl-0 = <&pflash_default_pins>;
75 /* Eraseblock at 0xfe0000 */
76 fis-index-block = <0x7F>;
82 pinctrl-0 = <&gpio0_default_pins>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dti,phy-am654-serdes.yaml56 - description: Clock output names for SERDES 0
86 reg = <0x900000 0x2000>;
96 mux-controls = <&serdes_mux 0>;
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dpm9g45.dts19 reg = <0x70000000 0x8000000>;
40 pinctrl_nand_rb: nand-rb-0 {
55 timer@0 {
57 reg = <0>, <1>;
67 pinctrl-0 = <
73 slot@0 {
74 reg = <0>;
91 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
95 reg = <0x3 0x0 0x800000>;
108 at91bootstrap@0 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm6115-tlmm.yaml59 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
101 reg = <0x500000 0x400000>,
102 <0x900000 0x400000>,
103 <0xd00000 0x400000>;
110 gpio-ranges = <&tlmm 0 0 114>;
/linux-6.12.1/arch/mips/boot/dts/mobileye/
Deyeq5.dtsi15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
34 reg = <0x8 0x04000000 0x0 0x1000000>;
37 reg = <0x8 0x05000000 0x0 0x1000000>;
40 reg = <0x8 0x06000000 0x0 0x100000>;
43 reg = <0x8 0x06100000 0x0 0x100000>;
47 reg = <0x8 0x06200000 0x0 0x100000>;
49 mhm_reserved_0: the-mhm-reserved-0@0 {
50 reg = <0x8 0x00000000 0x0 0x0000800>;
[all …]
/linux-6.12.1/sound/drivers/vx/
Dvx_cmd.c19 [CMD_VERSION] = { 0x010000, 2, RMH_SSIZE_FIXED, 1 },
20 [CMD_SUPPORTED] = { 0x020000, 1, RMH_SSIZE_FIXED, 2 },
21 [CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED, 1 },
22 [CMD_SEND_IRQA] = { 0x070001, 1, RMH_SSIZE_FIXED, 0 },
23 [CMD_IBL] = { 0x080000, 1, RMH_SSIZE_FIXED, 4 },
24 [CMD_ASYNC] = { 0x0A0000, 1, RMH_SSIZE_ARG, 0 },
25 [CMD_RES_PIPE] = { 0x400000, 1, RMH_SSIZE_FIXED, 0 },
26 [CMD_FREE_PIPE] = { 0x410000, 1, RMH_SSIZE_FIXED, 0 },
27 [CMD_CONF_PIPE] = { 0x42A101, 2, RMH_SSIZE_FIXED, 0 },
28 [CMD_ABORT_CONF_PIPE] = { 0x42A100, 2, RMH_SSIZE_FIXED, 0 },
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Damlogic-c3-c302x-aw409.dts22 memory@0 {
24 reg = <0x0 0x0 0x0 0x10000000>;
35 reg = <0x0 0x07f00000 0x0 0x900000>;
158 #size-cells = <0>;
160 pinctrl-0 = <&nand_pins>;
163 nand@0 {
164 reg = <0>;
169 partition@0 {
171 reg = <0x0 0x00200000>;
175 reg = <0x00200000 0x00400000>;
[all …]
Damlogic-c3-c308l-aw419.dts22 memory@0 {
24 reg = <0x0 0x0 0x0 0x80000000>;
35 reg = <0x0 0x07f00000 0x0 0x900000>;
158 #size-cells = <0>;
160 pinctrl-0 = <&nand_pins>;
163 nand@0 {
164 reg = <0>;
169 partition@0 {
171 reg = <0x0 0x00200000>;
175 reg = <0x00200000 0x00400000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-mdm9615.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0>;
45 #clock-cells = <0>;
66 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 2 0>;
76 reg = <0x02000000 0x1000>,
77 <0x02002000 0x1000>;
86 reg = <0x0200a000 0x100>;
88 cpu-offset = <0x80000>;
[all …]
Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x80000000 0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]
Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
45 reg = <0x0 0x0>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
86 reg = < 0x02080000 0x1000 >,
87 < 0x02081000 0x1000 >;
92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
[all …]
/linux-6.12.1/drivers/net/wireless/ath/wil6210/
Dwmi.c21 int agg_wsize; /* = 0; */
24 " 0 - use default; < 0 - don't auto-establish");
29 " 60G device led enablement. Set the led ID (0-2) to enable");
62 * AHB addresses starting from 0x880000
75 * 0x880000 .. 0xa80000 2Mb BAR0
76 * 0x800000 .. 0x808000 0x900000 .. 0x908000 32k DCCM
77 * 0x840000 .. 0x860000 0x908000 .. 0x928000 128k PERIPH
81 {0x000000, 0x040000, 0x8c0000, "fw_code", true, true},
83 {0x800000, 0x808000, 0x900000, "fw_data", true, true},
85 {0x840000, 0x860000, 0x908000, "fw_peri", true, true},
[all …]
/linux-6.12.1/drivers/pci/controller/
Dpcie-rockchip.h30 #define PCIE_CLIENT_BASE 0x0
31 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
32 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
33 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
34 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
35 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
39 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
[all …]

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