Lines Matching +full:0 +full:x900000

6  * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 	memory@0 {
36 		reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 				pinctrl-0 = <&ge0_rgmii_pins>;
69 				bm,pool-long = <0>;
78 				pinctrl-0 = <&ge1_rgmii_pins>;
102 					reg = <0x4c>;
107 					#size-cells = <0>;
110 					reg = <0x68>;
112 					wan_amber@0 {
114 						reg = <0x0>;
119 						reg = <0x1>;
124 						reg = <0x2>;
129 						reg = <0x3>;
134 						reg = <0x4>;
140 						reg = <0x5>;
145 						reg = <0x6>;
150 						reg = <0x7>;
155 						reg = <0x8>;
160 						reg = <0x9>;
177 		pinctrl-0 = <&keys_pin>;
183 			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
195 		pinctrl-0 = <&power_led_pin>;
217 	pcie@1,0 {
218 		/* Port 0, Lane 0 */
223 	pcie@2,0 {
224 		/* Port 0, Lane 1 */
229 	pcie@3,0 {
230 		/* Port 0, Lane 3 */
256 	flash@0 {
260 		reg = <0>; /* Chip select 0 */
268 	ethernet-switch@0 {
270 		reg = <0>;
274 			#size-cells = <0>;
276 			ethernet-port@0 {
277 				reg = <0>;
317 	nand@0 {
318 		reg = <0>;
319 		label = "pxa3xx_nand-0";
320 		nand-rb = <0>;
331 			partition@0 {
333 				reg = <0x0000000 0x100000>;  /* 1MB */
339 				reg = <0x100000 0x40000>;    /* 256KB */
344 				reg = <0x140000 0x40000>;    /* 256KB */
349 				reg = <0x900000 0x100000>;   /* 1MB */
356 				reg = <0xa00000 0x2800000>;  /* 40MB */
361 				reg = <0xd00000 0x2500000>;  /* 37MB */
367 				reg = <0x3200000 0x2800000>; /* 40MB */
372 				reg = <0x3500000 0x2500000>; /* 37MB */
380 				reg = <0x5a00000 0x2600000>;
391 				reg = <0x180000 0x780000>;   /* 7.5MB */