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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drockchip,rk3576-cru.yaml53 reg = <0xfd7c0000 0x5c000>;
Drockchip,rk3588-cru.yaml64 reg = <0xfd7c0000 0x5c000>;
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/clk/
Dclk_11_5_0_offset.h26 // base address: 0x5c000
27 …CLK1_0_CLK1_CLK_PLL_REQ 0x0410
28 …ne mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0
29 …CLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a
30 …ne mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0
31 …CLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454
32 …ne mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0
33 …CLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e
34 …ne mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
35 …CLK1_0_CLK1_CLK3_DS_CNTL 0x0461
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-mvebu-comphy.txt21 * Lane 0 (USB3/GbE)
26 - #size-cells: should be 0.
47 reg = <0x120000 0x6000>;
53 #size-cells = <0>;
55 CP11X_LABEL(comphy0): phy@0 {
56 reg = <0>;
68 reg = <0x18300 0x300>,
69 <0x1F000 0x400>,
70 <0x5C000 0x400>,
71 <0xe0178 0x8>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
66 #clock-cells = <0>;
89 #address-cells = <0>;
91 reg = <0x0 0xfff01000 0 0x1000>,
92 <0x0 0xfff02000 0 0x2000>,
[all …]
/linux-6.12.1/drivers/soc/tegra/cbb/
Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/linux-6.12.1/drivers/scsi/qla2xxx/
Dqla_fw.h14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
Dgcc-msm8953.c40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
[all …]
Dgcc-sa8775p.c74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x5000,
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtl8xxxu/
D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
20 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
21 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
22 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
23 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
24 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
25 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
26 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
27 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-base.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]