Lines Matching +full:0 +full:x5c000
54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
126 .enable_reg = 0x79000,
141 .l = 0x3c,
142 .alpha = 0x0,
143 .config_ctl_val = 0x20485699,
144 .config_ctl_hi_val = 0x00002261,
145 .config_ctl_hi1_val = 0x329a299c,
146 .user_ctl_val = 0x00000001,
147 .user_ctl_hi_val = 0x00000805,
148 .user_ctl_hi1_val = 0x00000000,
152 .offset = 0xa000,
158 .enable_reg = 0x79000,
173 .l = 0x1b,
174 .alpha = 0xb555,
175 .config_ctl_val = 0x20485699,
176 .config_ctl_hi_val = 0x00002261,
177 .config_ctl_hi1_val = 0x329a299c,
178 .user_ctl_val = 0x00000001,
179 .user_ctl_hi_val = 0x00000805,
180 .user_ctl_hi1_val = 0x00000000,
184 .offset = 0xb000,
190 .enable_reg = 0x79000,
204 .offset = 0x3000,
207 .enable_reg = 0x79000,
221 { 0x1, 2 },
226 .offset = 0x3000,
243 .offset = 0x4000,
246 .enable_reg = 0x79000,
260 .offset = 0x5000,
263 .enable_reg = 0x79000,
277 .offset = 0x6000,
280 .enable_reg = 0x79000,
294 { 0x1, 2 },
299 .offset = 0x6000,
316 .offset = 0x7000,
319 .enable_reg = 0x79000,
334 .l = 0x14,
335 .alpha = 0xd555,
336 .config_ctl_val = 0x20485699,
337 .config_ctl_hi_val = 0x00002261,
338 .config_ctl_hi1_val = 0x329a299c,
339 .user_ctl_val = 0x00000101,
340 .user_ctl_hi_val = 0x00000805,
341 .user_ctl_hi1_val = 0x00000000,
345 .offset = 0x8000,
351 .enable_reg = 0x79000,
365 { 0x1, 2 },
370 .offset = 0x8000,
389 .l = 0x4b,
390 .alpha = 0x0,
391 .config_ctl_val = 0x08200800,
392 .config_ctl_hi_val = 0x05022011,
393 .config_ctl_hi1_val = 0x08000000,
394 .user_ctl_val = 0x00000301,
398 .offset = 0x9000,
403 .enable_reg = 0x79000,
417 { 0x3, 4 },
422 .offset = 0x9000,
440 { P_BI_TCXO, 0 },
452 { P_BI_TCXO, 0 },
466 { P_BI_TCXO, 0 },
487 { P_BI_TCXO, 0 },
505 { P_BI_TCXO, 0 },
523 { P_BI_TCXO, 0 },
543 { P_BI_TCXO, 0 },
563 { P_BI_TCXO, 0 },
579 { P_BI_TCXO, 0 },
597 { P_BI_TCXO, 0 },
617 { P_BI_TCXO, 0 },
637 { P_BI_TCXO, 0 },
655 { P_BI_TCXO, 0 },
671 { P_BI_TCXO, 0 },
681 { P_BI_TCXO, 0 },
693 F(19200000, P_BI_TCXO, 1, 0, 0),
694 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
695 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
696 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
701 .cmd_rcgr = 0x5802c,
702 .mnd_width = 0,
715 F(19200000, P_BI_TCXO, 1, 0, 0),
716 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
721 .cmd_rcgr = 0x56000,
722 .mnd_width = 0,
735 .cmd_rcgr = 0x5c000,
736 .mnd_width = 0,
749 F(19200000, P_BI_TCXO, 1, 0, 0),
750 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
751 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
756 .cmd_rcgr = 0x59000,
757 .mnd_width = 0,
770 .cmd_rcgr = 0x5901c,
771 .mnd_width = 0,
784 .cmd_rcgr = 0x59038,
785 .mnd_width = 0,
798 .cmd_rcgr = 0x59054,
799 .mnd_width = 0,
812 F(19200000, P_BI_TCXO, 1, 0, 0),
819 .cmd_rcgr = 0x51000,
833 .cmd_rcgr = 0x5101c,
847 .cmd_rcgr = 0x51038,
861 .cmd_rcgr = 0x51054,
875 .cmd_rcgr = 0x51070,
889 F(19200000, P_BI_TCXO, 1, 0, 0),
890 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
891 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
896 .cmd_rcgr = 0x55024,
897 .mnd_width = 0,
910 F(19200000, P_BI_TCXO, 1, 0, 0),
911 F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
912 F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
913 F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
914 F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
919 .cmd_rcgr = 0x55004,
920 .mnd_width = 0,
934 F(19200000, P_BI_TCXO, 1, 0, 0),
935 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
936 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
937 F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
938 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
939 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
940 F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0),
941 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
942 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
943 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
944 F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
945 F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
946 F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0),
947 F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0),
952 .cmd_rcgr = 0x52004,
966 F(19200000, P_BI_TCXO, 1, 0, 0),
967 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
968 F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0),
969 F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
970 F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0),
975 .cmd_rcgr = 0x52094,
976 .mnd_width = 0,
989 .cmd_rcgr = 0x52024,
1003 .cmd_rcgr = 0x520b4,
1004 .mnd_width = 0,
1017 .cmd_rcgr = 0x52044,
1031 .cmd_rcgr = 0x520d4,
1032 .mnd_width = 0,
1045 F(19200000, P_BI_TCXO, 1, 0, 0),
1046 F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1047 F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1052 .cmd_rcgr = 0x52064,
1053 .mnd_width = 0,
1066 F(19200000, P_BI_TCXO, 1, 0, 0),
1067 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1068 F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
1073 .cmd_rcgr = 0x58010,
1074 .mnd_width = 0,
1087 F(19200000, P_BI_TCXO, 1, 0, 0),
1088 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1089 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1094 .cmd_rcgr = 0x2b13c,
1095 .mnd_width = 0,
1108 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1109 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1110 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1111 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1116 .cmd_rcgr = 0x4d004,
1130 .cmd_rcgr = 0x4e004,
1144 .cmd_rcgr = 0x4f004,
1158 F(19200000, P_BI_TCXO, 1, 0, 0),
1159 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1164 .cmd_rcgr = 0x20010,
1165 .mnd_width = 0,
1180 F(19200000, P_BI_TCXO, 1, 0, 0),
1185 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1188 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1192 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
1193 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
1205 .cmd_rcgr = 0x1f148,
1221 .cmd_rcgr = 0x1f278,
1237 .cmd_rcgr = 0x1f3a8,
1253 .cmd_rcgr = 0x1f4d8,
1269 .cmd_rcgr = 0x1f608,
1285 .cmd_rcgr = 0x1f738,
1301 .cmd_rcgr = 0x5301c,
1317 .cmd_rcgr = 0x5314c,
1333 .cmd_rcgr = 0x5327c,
1349 .cmd_rcgr = 0x533ac,
1365 .cmd_rcgr = 0x534dc,
1381 .cmd_rcgr = 0x5360c,
1394 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1395 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1396 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
1397 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
1402 .cmd_rcgr = 0x38028,
1416 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1417 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1418 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1419 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1420 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1425 .cmd_rcgr = 0x38010,
1426 .mnd_width = 0,
1440 F(19200000, P_BI_TCXO, 1, 0, 0),
1441 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1442 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1443 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1444 F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
1449 .cmd_rcgr = 0x1e00c,
1463 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1464 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1465 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1466 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1467 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1472 .cmd_rcgr = 0x45020,
1486 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1487 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1488 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1489 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1494 .cmd_rcgr = 0x45048,
1495 .mnd_width = 0,
1508 F(9600000, P_BI_TCXO, 2, 0, 0),
1509 F(19200000, P_BI_TCXO, 1, 0, 0),
1514 .cmd_rcgr = 0x4507c,
1515 .mnd_width = 0,
1528 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1529 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1530 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1535 .cmd_rcgr = 0x45060,
1536 .mnd_width = 0,
1549 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1550 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1551 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1552 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1557 .cmd_rcgr = 0x1a01c,
1571 F(19200000, P_BI_TCXO, 1, 0, 0),
1576 .cmd_rcgr = 0x1a034,
1577 .mnd_width = 0,
1590 .cmd_rcgr = 0x1a060,
1591 .mnd_width = 0,
1604 F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0),
1605 F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0),
1606 F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1607 F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1612 .cmd_rcgr = 0x58060,
1613 .mnd_width = 0,
1627 .reg = 0x2b154,
1628 .shift = 0,
1642 .reg = 0x1a04c,
1643 .shift = 0,
1657 .halt_reg = 0x1d004,
1659 .hwcg_reg = 0x1d004,
1662 .enable_reg = 0x1d004,
1663 .enable_mask = BIT(0),
1672 .halt_reg = 0x1d008,
1674 .hwcg_reg = 0x1d008,
1677 .enable_reg = 0x1d008,
1678 .enable_mask = BIT(0),
1687 .halt_reg = 0x71154,
1689 .hwcg_reg = 0x71154,
1692 .enable_reg = 0x71154,
1693 .enable_mask = BIT(0),
1702 .halt_reg = 0x23004,
1704 .hwcg_reg = 0x23004,
1707 .enable_reg = 0x79004,
1717 .halt_reg = 0x17070,
1719 .hwcg_reg = 0x17070,
1722 .enable_reg = 0x79004,
1732 .halt_reg = 0x1706c,
1734 .hwcg_reg = 0x1706c,
1737 .enable_reg = 0x79004,
1747 .halt_reg = 0x17008,
1749 .hwcg_reg = 0x17008,
1752 .enable_reg = 0x17008,
1753 .enable_mask = BIT(0),
1763 .halt_reg = 0x58044,
1766 .enable_reg = 0x58044,
1767 .enable_mask = BIT(0),
1781 .halt_reg = 0x56018,
1784 .enable_reg = 0x56018,
1785 .enable_mask = BIT(0),
1799 .halt_reg = 0x5c018,
1802 .enable_reg = 0x5c018,
1803 .enable_mask = BIT(0),
1817 .halt_reg = 0x52088,
1820 .enable_reg = 0x52088,
1821 .enable_mask = BIT(0),
1835 .halt_reg = 0x5208c,
1838 .enable_reg = 0x5208c,
1839 .enable_mask = BIT(0),
1853 .halt_reg = 0x52090,
1856 .enable_reg = 0x52090,
1857 .enable_mask = BIT(0),
1871 .halt_reg = 0x520f8,
1874 .enable_reg = 0x520f8,
1875 .enable_mask = BIT(0),
1889 .halt_reg = 0x59018,
1892 .enable_reg = 0x59018,
1893 .enable_mask = BIT(0),
1907 .halt_reg = 0x59034,
1910 .enable_reg = 0x59034,
1911 .enable_mask = BIT(0),
1925 .halt_reg = 0x59050,
1928 .enable_reg = 0x59050,
1929 .enable_mask = BIT(0),
1943 .halt_reg = 0x5906c,
1946 .enable_reg = 0x5906c,
1947 .enable_mask = BIT(0),
1961 .halt_reg = 0x51018,
1964 .enable_reg = 0x51018,
1965 .enable_mask = BIT(0),
1979 .halt_reg = 0x51034,
1982 .enable_reg = 0x51034,
1983 .enable_mask = BIT(0),
1997 .halt_reg = 0x51050,
2000 .enable_reg = 0x51050,
2001 .enable_mask = BIT(0),
2015 .halt_reg = 0x5106c,
2018 .enable_reg = 0x5106c,
2019 .enable_mask = BIT(0),
2033 .halt_reg = 0x51088,
2036 .enable_reg = 0x51088,
2037 .enable_mask = BIT(0),
2051 .halt_reg = 0x58054,
2054 .enable_reg = 0x58054,
2055 .enable_mask = BIT(0),
2064 .halt_reg = 0x5503c,
2067 .enable_reg = 0x5503c,
2068 .enable_mask = BIT(0),
2082 .halt_reg = 0x5501c,
2085 .enable_reg = 0x5501c,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x5805c,
2103 .enable_reg = 0x5805c,
2104 .enable_mask = BIT(0),
2113 .halt_reg = 0x5201c,
2116 .enable_reg = 0x5201c,
2117 .enable_mask = BIT(0),
2131 .halt_reg = 0x5207c,
2134 .enable_reg = 0x5207c,
2135 .enable_mask = BIT(0),
2149 .halt_reg = 0x520ac,
2152 .enable_reg = 0x520ac,
2153 .enable_mask = BIT(0),
2167 .halt_reg = 0x5203c,
2170 .enable_reg = 0x5203c,
2171 .enable_mask = BIT(0),
2185 .halt_reg = 0x52080,
2188 .enable_reg = 0x52080,
2189 .enable_mask = BIT(0),
2203 .halt_reg = 0x520cc,
2206 .enable_reg = 0x520cc,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x5205c,
2224 .enable_reg = 0x5205c,
2225 .enable_mask = BIT(0),
2239 .halt_reg = 0x52084,
2242 .enable_reg = 0x52084,
2243 .enable_mask = BIT(0),
2257 .halt_reg = 0x520ec,
2260 .enable_reg = 0x520ec,
2261 .enable_mask = BIT(0),
2275 .halt_reg = 0x58028,
2278 .enable_reg = 0x58028,
2279 .enable_mask = BIT(0),
2293 .halt_reg = 0x1a084,
2295 .hwcg_reg = 0x1a084,
2298 .enable_reg = 0x1a084,
2299 .enable_mask = BIT(0),
2313 .halt_reg = 0x1700c,
2315 .hwcg_reg = 0x1700c,
2318 .enable_reg = 0x1700c,
2319 .enable_mask = BIT(0),
2329 .reg = 0x17058,
2330 .shift = 0,
2345 .enable_reg = 0x79004,
2360 .halt_reg = 0x17020,
2362 .hwcg_reg = 0x17020,
2365 .enable_reg = 0x17020,
2366 .enable_mask = BIT(0),
2375 .halt_reg = 0x17074,
2377 .hwcg_reg = 0x17074,
2380 .enable_reg = 0x17074,
2381 .enable_mask = BIT(0),
2390 .halt_reg = 0x17064,
2392 .hwcg_reg = 0x17064,
2395 .enable_reg = 0x7900c,
2405 .halt_reg = 0x4d000,
2408 .enable_reg = 0x4d000,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x4e000,
2426 .enable_reg = 0x4e000,
2427 .enable_mask = BIT(0),
2441 .halt_reg = 0x4f000,
2444 .enable_reg = 0x4f000,
2445 .enable_mask = BIT(0),
2459 .halt_reg = 0x36004,
2461 .hwcg_reg = 0x36004,
2464 .enable_reg = 0x36004,
2465 .enable_mask = BIT(0),
2477 .enable_reg = 0x79004,
2494 .enable_reg = 0x79004,
2509 .halt_reg = 0x3600c,
2511 .hwcg_reg = 0x3600c,
2514 .enable_reg = 0x3600c,
2515 .enable_mask = BIT(0),
2524 .halt_reg = 0x36018,
2527 .enable_reg = 0x36018,
2528 .enable_mask = BIT(0),
2537 .halt_reg = 0x36048,
2539 .hwcg_reg = 0x36048,
2542 .enable_reg = 0x79004,
2552 .halt_reg = 0x2000c,
2555 .enable_reg = 0x2000c,
2556 .enable_mask = BIT(0),
2570 .halt_reg = 0x20004,
2572 .hwcg_reg = 0x20004,
2575 .enable_reg = 0x20004,
2576 .enable_mask = BIT(0),
2585 .halt_reg = 0x20008,
2588 .enable_reg = 0x20008,
2589 .enable_mask = BIT(0),
2598 .halt_reg = 0x21004,
2600 .hwcg_reg = 0x21004,
2603 .enable_reg = 0x79004,
2613 .halt_reg = 0x17014,
2615 .hwcg_reg = 0x17014,
2618 .enable_reg = 0x7900c,
2619 .enable_mask = BIT(0),
2628 .halt_reg = 0x17060,
2630 .hwcg_reg = 0x17060,
2633 .enable_reg = 0x7900c,
2643 .halt_reg = 0x17018,
2645 .hwcg_reg = 0x17018,
2648 .enable_reg = 0x7900c,
2658 .halt_reg = 0x36040,
2660 .hwcg_reg = 0x36040,
2663 .enable_reg = 0x7900c,
2673 .halt_reg = 0x17010,
2675 .hwcg_reg = 0x17010,
2678 .enable_reg = 0x79004,
2688 .halt_reg = 0x1f014,
2691 .enable_reg = 0x7900c,
2701 .halt_reg = 0x1f00c,
2704 .enable_reg = 0x7900c,
2714 .halt_reg = 0x1f144,
2717 .enable_reg = 0x7900c,
2732 .halt_reg = 0x1f274,
2735 .enable_reg = 0x7900c,
2750 .halt_reg = 0x1f3a4,
2753 .enable_reg = 0x7900c,
2768 .halt_reg = 0x1f4d4,
2771 .enable_reg = 0x7900c,
2786 .halt_reg = 0x1f604,
2789 .enable_reg = 0x7900c,
2804 .halt_reg = 0x1f734,
2807 .enable_reg = 0x7900c,
2822 .halt_reg = 0x53014,
2825 .enable_reg = 0x7900c,
2835 .halt_reg = 0x5300c,
2838 .enable_reg = 0x7900c,
2848 .halt_reg = 0x53018,
2851 .enable_reg = 0x7900c,
2866 .halt_reg = 0x53148,
2869 .enable_reg = 0x7900c,
2884 .halt_reg = 0x53278,
2887 .enable_reg = 0x7900c,
2902 .halt_reg = 0x533a8,
2905 .enable_reg = 0x7900c,
2920 .halt_reg = 0x534d8,
2923 .enable_reg = 0x7900c,
2938 .halt_reg = 0x53608,
2941 .enable_reg = 0x7900c,
2956 .halt_reg = 0x1f004,
2958 .hwcg_reg = 0x1f004,
2961 .enable_reg = 0x7900c,
2971 .halt_reg = 0x1f008,
2973 .hwcg_reg = 0x1f008,
2976 .enable_reg = 0x7900c,
2986 .halt_reg = 0x53004,
2988 .hwcg_reg = 0x53004,
2991 .enable_reg = 0x7900c,
3001 .halt_reg = 0x53008,
3003 .hwcg_reg = 0x53008,
3006 .enable_reg = 0x7900c,
3016 .halt_reg = 0x38008,
3019 .enable_reg = 0x38008,
3020 .enable_mask = BIT(0),
3029 .halt_reg = 0x38004,
3032 .enable_reg = 0x38004,
3033 .enable_mask = BIT(0),
3047 .halt_reg = 0x3800c,
3049 .hwcg_reg = 0x3800c,
3052 .enable_reg = 0x3800c,
3053 .enable_mask = BIT(0),
3067 .halt_reg = 0x1e008,
3070 .enable_reg = 0x1e008,
3071 .enable_mask = BIT(0),
3080 .halt_reg = 0x1e004,
3083 .enable_reg = 0x1e004,
3084 .enable_mask = BIT(0),
3098 .halt_reg = 0x2b06c,
3100 .hwcg_reg = 0x2b06c,
3103 .enable_reg = 0x79004,
3104 .enable_mask = BIT(0),
3118 .halt_reg = 0x45098,
3121 .enable_reg = 0x45098,
3122 .enable_mask = BIT(0),
3136 .halt_reg = 0x1a080,
3138 .hwcg_reg = 0x1a080,
3141 .enable_reg = 0x1a080,
3142 .enable_mask = BIT(0),
3156 .halt_reg = 0x45014,
3158 .hwcg_reg = 0x45014,
3161 .enable_reg = 0x45014,
3162 .enable_mask = BIT(0),
3171 .halt_reg = 0x45010,
3173 .hwcg_reg = 0x45010,
3176 .enable_reg = 0x45010,
3177 .enable_mask = BIT(0),
3191 .halt_reg = 0x45044,
3193 .hwcg_reg = 0x45044,
3196 .enable_reg = 0x45044,
3197 .enable_mask = BIT(0),
3211 .halt_reg = 0x45078,
3213 .hwcg_reg = 0x45078,
3216 .enable_reg = 0x45078,
3217 .enable_mask = BIT(0),
3231 .halt_reg = 0x4501c,
3234 .enable_reg = 0x4501c,
3235 .enable_mask = BIT(0),
3244 .halt_reg = 0x45018,
3247 .enable_reg = 0x45018,
3248 .enable_mask = BIT(0),
3257 .halt_reg = 0x45040,
3259 .hwcg_reg = 0x45040,
3262 .enable_reg = 0x45040,
3263 .enable_mask = BIT(0),
3277 .halt_reg = 0x1a010,
3280 .enable_reg = 0x1a010,
3281 .enable_mask = BIT(0),
3295 .halt_reg = 0x1a018,
3298 .enable_reg = 0x1a018,
3299 .enable_mask = BIT(0),
3313 .halt_reg = 0x1a014,
3316 .enable_reg = 0x1a014,
3317 .enable_mask = BIT(0),
3326 .halt_reg = 0x8c000,
3329 .enable_reg = 0x8c000,
3330 .enable_mask = BIT(0),
3339 .halt_reg = 0x8c00c,
3342 .enable_reg = 0x8c00c,
3343 .enable_mask = BIT(0),
3352 .halt_reg = 0x8c010,
3355 .enable_reg = 0x8c010,
3356 .enable_mask = BIT(0),
3365 .halt_reg = 0x1a054,
3368 .enable_reg = 0x1a054,
3369 .enable_mask = BIT(0),
3383 .halt_reg = 0x1a058,
3385 .hwcg_reg = 0x1a058,
3388 .enable_reg = 0x1a058,
3389 .enable_mask = BIT(0),
3398 .halt_reg = 0x6e008,
3401 .enable_reg = 0x6e008,
3402 .enable_mask = BIT(0),
3411 .halt_reg = 0x6e010,
3414 .enable_reg = 0x6e010,
3415 .enable_mask = BIT(0),
3424 .halt_reg = 0x6e004,
3427 .enable_reg = 0x6e004,
3428 .enable_mask = BIT(0),
3437 .halt_reg = 0x17004,
3439 .hwcg_reg = 0x17004,
3442 .enable_reg = 0x17004,
3443 .enable_mask = BIT(0),
3453 .halt_reg = 0x1701c,
3455 .hwcg_reg = 0x1701c,
3458 .enable_reg = 0x1701c,
3459 .enable_mask = BIT(0),
3468 .halt_reg = 0x17068,
3470 .hwcg_reg = 0x17068,
3473 .enable_reg = 0x79004,
3483 .halt_reg = 0x580a4,
3485 .hwcg_reg = 0x580a4,
3488 .enable_reg = 0x580a4,
3489 .enable_mask = BIT(0),
3503 .halt_reg = 0x5808c,
3506 .enable_reg = 0x5808c,
3507 .enable_mask = BIT(0),
3521 .halt_reg = 0x17024,
3524 .enable_reg = 0x17024,
3525 .enable_mask = BIT(0),
3534 .gdscr = 0x1a004,
3543 .gdscr = 0x45004,
3551 .gdscr = 0x58004,
3559 .gdscr = 0x5807c,
3567 .gdscr = 0x58098,
3576 .gdscr = 0x7d074,
3585 .gdscr = 0x7d078,
3594 .gdscr = 0x7d060,
3603 .gdscr = 0x7d07c,
3798 [GCC_MMSS_BCR] = { 0x17000 },
3799 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3800 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3801 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
3802 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3803 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3804 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3805 [GCC_SDCC2_BCR] = { 0x1e000 },
3806 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
3807 [GCC_PDM_BCR] = { 0x20000 },
3808 [GCC_GPU_BCR] = { 0x36000 },
3809 [GCC_SDCC1_BCR] = { 0x38000 },
3810 [GCC_UFS_PHY_BCR] = { 0x45000 },
3811 [GCC_CAMSS_TFE_BCR] = { 0x52000 },
3812 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 },
3813 [GCC_CAMSS_OPE_BCR] = { 0x55000 },
3814 [GCC_CAMSS_TOP_BCR] = { 0x58000 },
3815 [GCC_VENUS_BCR] = { 0x58078 },
3816 [GCC_VCODEC0_BCR] = { 0x58094 },
3817 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3852 .max_register = 0xc7000,
3886 qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ in gcc_sm6375_probe()
3887 qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ in gcc_sm6375_probe()
3888 qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ in gcc_sm6375_probe()