Lines Matching +full:0 +full:x5c000
40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
125 .offset = 0x22000,
143 .offset = 0x22000,
157 .offset = 0x24000,
160 .enable_reg = 0x45000,
174 .offset = 0x24000,
187 .offset = 0x37000,
190 .enable_reg = 0x45000,
217 .offset = 0x37000,
230 { P_XO, 0 },
236 { P_XO, 0 },
248 { P_XO, 0 },
260 F(19200000, P_XO, 1, 0, 0),
261 F(400000000, P_GPLL0, 2, 0, 0),
262 F(576000000, P_GPLL4, 2, 0, 0),
267 .cmd_rcgr = 0x78008,
279 .cmd_rcgr = 0x79008,
292 F(19200000, P_XO, 1, 0, 0),
293 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
294 F(50000000, P_GPLL0, 16, 0, 0),
295 F(100000000, P_GPLL0, 8, 0, 0),
296 F(133330000, P_GPLL0, 6, 0, 0),
301 .cmd_rcgr = 0x46000,
314 F(19200000, P_XO, 1, 0, 0),
315 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
316 F(50000000, P_GPLL0, 16, 0, 0),
321 .cmd_rcgr = 0x0200c,
334 .cmd_rcgr = 0x03000,
347 .cmd_rcgr = 0x04000,
360 .cmd_rcgr = 0x05000,
373 .cmd_rcgr = 0x0c00c,
386 .cmd_rcgr = 0x0d000,
399 .cmd_rcgr = 0x0f000,
412 .cmd_rcgr = 0x18000,
426 F(4800000, P_XO, 4, 0, 0),
427 F(9600000, P_XO, 2, 0, 0),
430 F(19200000, P_XO, 1, 0, 0),
432 F(50000000, P_GPLL0, 16, 0, 0),
437 .cmd_rcgr = 0x02024,
451 .cmd_rcgr = 0x03014,
465 .cmd_rcgr = 0x04024,
479 .cmd_rcgr = 0x05024,
493 .cmd_rcgr = 0x0c024,
507 .cmd_rcgr = 0x0d014,
521 .cmd_rcgr = 0x0f024,
535 .cmd_rcgr = 0x18024,
553 F(19200000, P_XO, 1, 0, 0),
569 .cmd_rcgr = 0x02044,
583 .cmd_rcgr = 0x03034,
597 .cmd_rcgr = 0x0c044,
611 .cmd_rcgr = 0x0d034,
625 { P_XO, 0 },
631 { P_XO, 0 },
643 .cmd_rcgr = 0x4d044,
656 .cmd_rcgr = 0x4d0b0,
669 { P_XO, 0 },
685 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
686 F(100000000, P_GPLL0, 8, 0, 0),
687 F(200000000, P_GPLL0, 4, 0, 0),
688 F(266670000, P_GPLL0, 3, 0, 0),
693 .cmd_rcgr = 0x54000,
707 .cmd_rcgr = 0x55000,
721 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
722 F(80000000, P_GPLL0, 10, 0, 0),
727 .cmd_rcgr = 0x5a000,
740 { P_XO, 0 },
754 F(19200000, P_XO, 1, 0, 0),
760 .cmd_rcgr = 0x51000,
774 { P_XO, 0 },
790 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
791 F(200000000, P_GPLL0, 4, 0, 0),
792 F(266670000, P_GPLL0, 3, 0, 0),
793 F(320000000, P_GPLL0, 2.5, 0, 0),
794 F(400000000, P_GPLL0, 2, 0, 0),
795 F(465000000, P_GPLL2, 2, 0, 0),
800 .cmd_rcgr = 0x58018,
813 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
814 F(80000000, P_GPLL0, 10, 0, 0),
815 F(100000000, P_GPLL0, 8, 0, 0),
816 F(160000000, P_GPLL0, 5, 0, 0),
821 .cmd_rcgr = 0x16004,
834 { P_XO, 0 },
841 { P_XO, 0 },
855 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
856 F(200000000, P_GPLL0, 4, 0, 0),
857 F(310000000, P_GPLL2, 3, 0, 0),
858 F(400000000, P_GPLL0, 2, 0, 0),
859 F(465000000, P_GPLL2, 2, 0, 0),
864 .cmd_rcgr = 0x4e020,
877 .cmd_rcgr = 0x4f020,
890 .cmd_rcgr = 0x3c020,
903 { P_XO, 0 },
919 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
920 F(133330000, P_GPLL0, 6, 0, 0),
921 F(200000000, P_GPLL0, 4, 0, 0),
922 F(266670000, P_GPLL0, 3, 0, 0),
923 F(310000000, P_GPLL2, 3, 0, 0),
928 .cmd_rcgr = 0x58084,
941 .cmd_rcgr = 0x58094,
954 .cmd_rcgr = 0x580a4,
967 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
968 F(200000000, P_GPLL0, 4, 0, 0),
969 F(266670000, P_GPLL0, 3, 0, 0),
974 .cmd_rcgr = 0x4e000,
987 .cmd_rcgr = 0x4f000,
1000 .cmd_rcgr = 0x4f05c,
1013 { P_XO, 0 },
1023 F(19200000, P_XO, 1, 0, 0),
1028 .cmd_rcgr = 0x4d05c,
1041 .cmd_rcgr = 0x4d0a8,
1054 { P_XO, 0 },
1074 F(19200000, P_XO, 1, 0, 0),
1075 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1076 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1077 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1078 F(133330000, P_GPLL0_DIV2, 3, 0, 0),
1079 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1080 F(200000000, P_GPLL0_DIV2, 2, 0, 0),
1081 F(266670000, P_GPLL0, 3.0, 0, 0),
1082 F(320000000, P_GPLL0, 2.5, 0, 0),
1083 F(400000000, P_GPLL0, 2, 0, 0),
1084 F(460800000, P_GPLL4, 2.5, 0, 0),
1085 F(510000000, P_GPLL3, 2, 0, 0),
1086 F(560000000, P_GPLL3, 2, 0, 0),
1087 F(600000000, P_GPLL3, 2, 0, 0),
1088 F(650000000, P_GPLL3, 2, 0, 0),
1089 F(685000000, P_GPLL3, 2, 0, 0),
1090 F(725000000, P_GPLL3, 2, 0, 0),
1095 .cmd_rcgr = 0x59000,
1109 F(19200000, P_XO, 1, 0, 0),
1114 .cmd_rcgr = 0x08004,
1128 .cmd_rcgr = 0x09004,
1142 .cmd_rcgr = 0x0a004,
1156 { P_XO, 0 },
1172 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
1173 F(133330000, P_GPLL0, 6, 0, 0),
1174 F(200000000, P_GPLL0, 4, 0, 0),
1175 F(266670000, P_GPLL0, 3, 0, 0),
1176 F(310000000, P_GPLL2, 3, 0, 0),
1177 F(320000000, P_GPLL0, 2.5, 0, 0),
1182 .cmd_rcgr = 0x57000,
1195 { P_XO, 0 },
1216 F(33330000, P_GPLL0_DIV2, 12, 0, 0),
1218 F(66667000, P_GPLL0, 12, 0, 0),
1223 .cmd_rcgr = 0x52000,
1237 .cmd_rcgr = 0x53000,
1251 .cmd_rcgr = 0x5c000,
1265 .cmd_rcgr = 0x5e000,
1279 { P_XO, 0 },
1293 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1294 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1295 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1296 F(200000000, P_GPLL0, 4, 0, 0),
1297 F(266670000, P_GPLL0, 3, 0, 0),
1298 F(320000000, P_GPLL0, 2.5, 0, 0),
1299 F(400000000, P_GPLL0, 2, 0, 0),
1304 .cmd_rcgr = 0x4d014,
1317 { P_XO, 0 },
1323 { P_XO, 0 },
1335 .cmd_rcgr = 0x4d000,
1349 .cmd_rcgr = 0x4d0b8,
1363 F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
1364 F(64000000, P_GPLL0, 12.5, 0, 0),
1369 .cmd_rcgr = 0x44010,
1382 F(19200000, P_XO, 1, 0, 0),
1383 F(50000000, P_GPLL0, 16, 0, 0),
1388 .cmd_rcgr = 0x3a00c,
1401 { P_XO, 0 },
1415 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1416 F(160000000, P_GPLL0, 5, 0, 0),
1417 F(270000000, P_GPLL6, 4, 0, 0),
1422 .cmd_rcgr = 0x5d000,
1435 { P_XO, 0 },
1452 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1453 F(50000000, P_GPLL0, 16, 0, 0),
1454 F(100000000, P_GPLL0, 8, 0, 0),
1455 F(177770000, P_GPLL0, 4.5, 0, 0),
1456 F(192000000, P_GPLL4, 6, 0, 0),
1457 F(384000000, P_GPLL4, 3, 0, 0),
1462 .cmd_rcgr = 0x42004,
1479 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1480 F(50000000, P_GPLL0, 16, 0, 0),
1481 F(100000000, P_GPLL0, 8, 0, 0),
1482 F(177770000, P_GPLL0, 4.5, 0, 0),
1483 F(192000000, P_GPLL4, 6, 0, 0),
1484 F(200000000, P_GPLL0, 4, 0, 0),
1489 .cmd_rcgr = 0x43004,
1503 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1504 F(100000000, P_GPLL0, 8, 0, 0),
1505 F(133330000, P_GPLL0, 6, 0, 0),
1510 .cmd_rcgr = 0x3f00c,
1523 { P_XO, 0 },
1539 F(19200000, P_XO, 1, 0, 0),
1545 .cmd_rcgr = 0x3f020,
1559 { P_XO, 0 },
1569 F(19200000, P_XO, 1, 0, 0),
1574 .cmd_rcgr = 0x3f05c,
1588 { P_XO, 0 },
1604 F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
1605 F(228570000, P_GPLL0, 3.5, 0, 0),
1606 F(310000000, P_GPLL2, 3, 0, 0),
1607 F(360000000, P_GPLL6, 3, 0, 0),
1608 F(400000000, P_GPLL0, 2, 0, 0),
1609 F(465000000, P_GPLL2, 2, 0, 0),
1610 F(540000000, P_GPLL6, 2, 0, 0),
1615 .cmd_rcgr = 0x4c000,
1628 { P_XO, 0 },
1646 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1647 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1648 F(133330000, P_GPLL0, 6, 0, 0),
1649 F(160000000, P_GPLL0, 5, 0, 0),
1650 F(200000000, P_GPLL0, 4, 0, 0),
1651 F(266670000, P_GPLL0, 3, 0, 0),
1652 F(310000000, P_GPLL2, 3, 0, 0),
1653 F(400000000, P_GPLL0, 2, 0, 0),
1654 F(465000000, P_GPLL2, 2, 0, 0),
1659 .cmd_rcgr = 0x58000,
1672 .cmd_rcgr = 0x58054,
1685 { P_XO, 0 },
1690 F(19200000, P_XO, 1, 0, 0),
1695 .cmd_rcgr = 0x4d02c,
1708 .halt_reg = 0x78004,
1711 .enable_reg = 0x78004,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x79004,
1729 .enable_reg = 0x79004,
1730 .enable_mask = BIT(0),
1744 .halt_reg = 0x4601c,
1747 .enable_reg = 0x45004,
1762 .halt_reg = 0x46020,
1765 .enable_reg = 0x45004,
1775 .halt_reg = 0x12018,
1778 .enable_reg = 0x4500c,
1788 .halt_reg = 0x59034,
1791 .enable_reg = 0x59034,
1792 .enable_mask = BIT(0),
1801 .halt_reg = 0x59030,
1804 .enable_reg = 0x59030,
1805 .enable_mask = BIT(0),
1814 .halt_reg = 0x01008,
1817 .enable_reg = 0x45004,
1827 .halt_reg = 0x0b008,
1830 .enable_reg = 0x45004,
1840 .halt_reg = 0x02008,
1843 .enable_reg = 0x02008,
1844 .enable_mask = BIT(0),
1858 .halt_reg = 0x03010,
1861 .enable_reg = 0x03010,
1862 .enable_mask = BIT(0),
1876 .halt_reg = 0x04020,
1879 .enable_reg = 0x04020,
1880 .enable_mask = BIT(0),
1894 .halt_reg = 0x05020,
1897 .enable_reg = 0x05020,
1898 .enable_mask = BIT(0),
1912 .halt_reg = 0x0c008,
1915 .enable_reg = 0x0c008,
1916 .enable_mask = BIT(0),
1930 .halt_reg = 0x0d010,
1933 .enable_reg = 0x0d010,
1934 .enable_mask = BIT(0),
1948 .halt_reg = 0x0f020,
1951 .enable_reg = 0x0f020,
1952 .enable_mask = BIT(0),
1966 .halt_reg = 0x18020,
1969 .enable_reg = 0x18020,
1970 .enable_mask = BIT(0),
1984 .halt_reg = 0x02004,
1987 .enable_reg = 0x02004,
1988 .enable_mask = BIT(0),
2002 .halt_reg = 0x0300c,
2005 .enable_reg = 0x0300c,
2006 .enable_mask = BIT(0),
2020 .halt_reg = 0x0401c,
2023 .enable_reg = 0x0401c,
2024 .enable_mask = BIT(0),
2038 .halt_reg = 0x0501c,
2041 .enable_reg = 0x0501c,
2042 .enable_mask = BIT(0),
2056 .halt_reg = 0x0c004,
2059 .enable_reg = 0x0c004,
2060 .enable_mask = BIT(0),
2074 .halt_reg = 0x0d00c,
2077 .enable_reg = 0x0d00c,
2078 .enable_mask = BIT(0),
2092 .halt_reg = 0x0f01c,
2095 .enable_reg = 0x0f01c,
2096 .enable_mask = BIT(0),
2110 .halt_reg = 0x1801c,
2113 .enable_reg = 0x1801c,
2114 .enable_mask = BIT(0),
2128 .halt_reg = 0x0203c,
2131 .enable_reg = 0x0203c,
2132 .enable_mask = BIT(0),
2146 .halt_reg = 0x0302c,
2149 .enable_reg = 0x0302c,
2150 .enable_mask = BIT(0),
2164 .halt_reg = 0x0c03c,
2167 .enable_reg = 0x0c03c,
2168 .enable_mask = BIT(0),
2182 .halt_reg = 0x0d02c,
2185 .enable_reg = 0x0d02c,
2186 .enable_mask = BIT(0),
2200 .halt_reg = 0x1300c,
2203 .enable_reg = 0x45004,
2213 .halt_reg = 0x56004,
2216 .enable_reg = 0x56004,
2217 .enable_mask = BIT(0),
2226 .halt_reg = 0x5101c,
2229 .enable_reg = 0x5101c,
2230 .enable_mask = BIT(0),
2244 .halt_reg = 0x51018,
2247 .enable_reg = 0x51018,
2248 .enable_mask = BIT(0),
2262 .halt_reg = 0x58040,
2265 .enable_reg = 0x58040,
2266 .enable_mask = BIT(0),
2280 .halt_reg = 0x58064,
2283 .enable_reg = 0x58064,
2284 .enable_mask = BIT(0),
2293 .halt_reg = 0x5803c,
2296 .enable_reg = 0x5803c,
2297 .enable_mask = BIT(0),
2311 .halt_reg = 0x4e040,
2314 .enable_reg = 0x4e040,
2315 .enable_mask = BIT(0),
2329 .halt_reg = 0x4f040,
2332 .enable_reg = 0x4f040,
2333 .enable_mask = BIT(0),
2347 .halt_reg = 0x3c040,
2350 .enable_reg = 0x3c040,
2351 .enable_mask = BIT(0),
2365 .halt_reg = 0x4e03c,
2368 .enable_reg = 0x4e03c,
2369 .enable_mask = BIT(0),
2383 .halt_reg = 0x4f03c,
2386 .enable_reg = 0x4f03c,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x3c03c,
2404 .enable_reg = 0x3c03c,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x58090,
2422 .enable_reg = 0x58090,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x580a0,
2440 .enable_reg = 0x580a0,
2441 .enable_mask = BIT(0),
2455 .halt_reg = 0x580b0,
2458 .enable_reg = 0x580b0,
2459 .enable_mask = BIT(0),
2473 .halt_reg = 0x4e048,
2476 .enable_reg = 0x4e048,
2477 .enable_mask = BIT(0),
2491 .halt_reg = 0x4f048,
2494 .enable_reg = 0x4f048,
2495 .enable_mask = BIT(0),
2509 .halt_reg = 0x3c048,
2512 .enable_reg = 0x3c048,
2513 .enable_mask = BIT(0),
2527 .halt_reg = 0x4e01c,
2530 .enable_reg = 0x4e01c,
2531 .enable_mask = BIT(0),
2545 .halt_reg = 0x4f01c,
2548 .enable_reg = 0x4f01c,
2549 .enable_mask = BIT(0),
2563 .halt_reg = 0x4f068,
2566 .enable_reg = 0x4f068,
2567 .enable_mask = BIT(0),
2581 .halt_reg = 0x4e058,
2584 .enable_reg = 0x4e058,
2585 .enable_mask = BIT(0),
2599 .halt_reg = 0x4f058,
2602 .enable_reg = 0x4f058,
2603 .enable_mask = BIT(0),
2617 .halt_reg = 0x3c058,
2620 .enable_reg = 0x3c058,
2621 .enable_mask = BIT(0),
2635 .halt_reg = 0x4e050,
2638 .enable_reg = 0x4e050,
2639 .enable_mask = BIT(0),
2653 .halt_reg = 0x4f050,
2656 .enable_reg = 0x4f050,
2657 .enable_mask = BIT(0),
2671 .halt_reg = 0x3c050,
2674 .enable_reg = 0x3c050,
2675 .enable_mask = BIT(0),
2689 .halt_reg = 0x58050,
2692 .enable_reg = 0x58050,
2693 .enable_mask = BIT(0),
2707 .halt_reg = 0x58074,
2710 .enable_reg = 0x58074,
2711 .enable_mask = BIT(0),
2725 .halt_reg = 0x54018,
2728 .enable_reg = 0x54018,
2729 .enable_mask = BIT(0),
2743 .halt_reg = 0x55018,
2746 .enable_reg = 0x55018,
2747 .enable_mask = BIT(0),
2761 .halt_reg = 0x50004,
2764 .enable_reg = 0x50004,
2765 .enable_mask = BIT(0),
2779 .halt_reg = 0x57020,
2782 .enable_reg = 0x57020,
2783 .enable_mask = BIT(0),
2797 .halt_reg = 0x57024,
2800 .enable_reg = 0x57024,
2801 .enable_mask = BIT(0),
2815 .halt_reg = 0x57028,
2818 .enable_reg = 0x57028,
2819 .enable_mask = BIT(0),
2828 .halt_reg = 0x52018,
2831 .enable_reg = 0x52018,
2832 .enable_mask = BIT(0),
2846 .halt_reg = 0x53018,
2849 .enable_reg = 0x53018,
2850 .enable_mask = BIT(0),
2864 .halt_reg = 0x5c018,
2867 .enable_reg = 0x5c018,
2868 .enable_mask = BIT(0),
2882 .halt_reg = 0x5e018,
2885 .enable_reg = 0x5e018,
2886 .enable_mask = BIT(0),
2900 .halt_reg = 0x5600c,
2903 .enable_reg = 0x5600c,
2904 .enable_mask = BIT(0),
2918 .halt_reg = 0x5a014,
2921 .enable_reg = 0x5a014,
2922 .enable_mask = BIT(0),
2936 .halt_reg = 0x58044,
2939 .enable_reg = 0x58044,
2940 .enable_mask = BIT(0),
2954 .halt_reg = 0x58048,
2957 .enable_reg = 0x58048,
2958 .enable_mask = BIT(0),
2967 .halt_reg = 0x58038,
2970 .enable_reg = 0x58038,
2971 .enable_mask = BIT(0),
2985 .halt_reg = 0x58060,
2988 .enable_reg = 0x58060,
2989 .enable_mask = BIT(0),
3003 .halt_reg = 0x58068,
3006 .enable_reg = 0x58068,
3007 .enable_mask = BIT(0),
3016 .halt_reg = 0x5805c,
3019 .enable_reg = 0x5805c,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x12040,
3037 .enable_reg = 0x4500c,
3047 .halt_reg = 0x16024,
3050 .enable_reg = 0x45004,
3051 .enable_mask = BIT(0),
3060 .halt_reg = 0x16020,
3063 .enable_reg = 0x45004,
3073 .halt_reg = 0x1601c,
3076 .enable_reg = 0x45004,
3091 .halt_reg = 0x77004,
3094 .enable_reg = 0x77004,
3095 .enable_mask = BIT(0),
3104 .halt_reg = 0x08000,
3107 .enable_reg = 0x08000,
3108 .enable_mask = BIT(0),
3122 .halt_reg = 0x09000,
3125 .enable_reg = 0x09000,
3126 .enable_mask = BIT(0),
3140 .halt_reg = 0x0a000,
3143 .enable_reg = 0x0a000,
3144 .enable_mask = BIT(0),
3158 .halt_reg = 0x12034,
3161 .enable_reg = 0x4500c,
3171 .halt_reg = 0x1201c,
3174 .enable_reg = 0x4500c,
3184 .halt_reg = 0x4d07c,
3187 .enable_reg = 0x4d07c,
3188 .enable_mask = BIT(0),
3197 .halt_reg = 0x4d080,
3200 .enable_reg = 0x4d080,
3201 .enable_mask = BIT(0),
3210 .halt_reg = 0x4d094,
3213 .enable_reg = 0x4d094,
3214 .enable_mask = BIT(0),
3228 .halt_reg = 0x4d0a0,
3231 .enable_reg = 0x4d0a0,
3232 .enable_mask = BIT(0),
3246 .halt_reg = 0x4d098,
3249 .enable_reg = 0x4d098,
3250 .enable_mask = BIT(0),
3264 .halt_reg = 0x4d09c,
3267 .enable_reg = 0x4d09c,
3268 .enable_mask = BIT(0),
3282 .halt_reg = 0x4d088,
3285 .enable_reg = 0x4d088,
3286 .enable_mask = BIT(0),
3300 .halt_reg = 0x4d084,
3303 .enable_reg = 0x4d084,
3304 .enable_mask = BIT(0),
3318 .halt_reg = 0x4d0a4,
3321 .enable_reg = 0x4d0a4,
3322 .enable_mask = BIT(0),
3336 .halt_reg = 0x4d090,
3339 .enable_reg = 0x4d090,
3340 .enable_mask = BIT(0),
3354 .halt_reg = 0x49000,
3357 .enable_reg = 0x49000,
3358 .enable_mask = BIT(0),
3367 .halt_reg = 0x49004,
3370 .enable_reg = 0x49004,
3371 .enable_mask = BIT(0),
3380 .halt_reg = 0x59028,
3383 .enable_reg = 0x59028,
3384 .enable_mask = BIT(0),
3393 .halt_reg = 0x59044,
3396 .enable_reg = 0x59044,
3397 .enable_mask = BIT(0),
3410 .halt_reg = 0x59020,
3413 .enable_reg = 0x59020,
3414 .enable_mask = BIT(0),
3428 .halt_reg = 0x59040,
3431 .enable_reg = 0x59040,
3432 .enable_mask = BIT(0),
3441 .halt_reg = 0x3f038,
3444 .enable_reg = 0x3f038,
3445 .enable_mask = BIT(0),
3459 .halt_reg = 0x4400c,
3462 .enable_reg = 0x4400c,
3463 .enable_mask = BIT(0),
3477 .halt_reg = 0x44004,
3480 .enable_reg = 0x44004,
3481 .enable_mask = BIT(0),
3490 .halt_reg = 0x13004,
3493 .enable_reg = 0x45004,
3503 .halt_reg = 0x29084,
3506 .enable_reg = 0x45004,
3516 .halt_reg = 0,
3519 .enable_reg = 0x41030,
3520 .enable_mask = BIT(0),
3529 .halt_reg = 0x3a004,
3532 .enable_reg = 0x3a004,
3533 .enable_mask = BIT(0),
3547 .halt_reg = 0x5d014,
3550 .enable_reg = 0x5d014,
3551 .enable_mask = BIT(0),
3565 .halt_reg = 0x4201c,
3568 .enable_reg = 0x4201c,
3569 .enable_mask = BIT(0),
3578 .halt_reg = 0x4301c,
3581 .enable_reg = 0x4301c,
3582 .enable_mask = BIT(0),
3591 .halt_reg = 0x42018,
3594 .enable_reg = 0x42018,
3595 .enable_mask = BIT(0),
3609 .halt_reg = 0x43018,
3612 .enable_reg = 0x43018,
3613 .enable_mask = BIT(0),
3627 .halt_reg = 0x12038,
3630 .enable_reg = 0x4500c,
3640 .halt_reg = 0x3f000,
3643 .enable_reg = 0x3f000,
3644 .enable_mask = BIT(0),
3658 .halt_reg = 0x3f008,
3661 .enable_reg = 0x3f008,
3662 .enable_mask = BIT(0),
3676 .halt_reg = 0x3f004,
3679 .enable_reg = 0x3f004,
3680 .enable_mask = BIT(0),
3689 .halt_reg = 0x3f044,
3692 .enable_reg = 0x3f044,
3693 .enable_mask = BIT(0),
3707 .halt_reg = 0,
3710 .enable_reg = 0x3f040,
3711 .enable_mask = BIT(0),
3720 .halt_reg = 0x3f080,
3723 .enable_reg = 0x3f080,
3724 .enable_mask = BIT(0),
3733 .halt_reg = 0,
3736 .enable_reg = 0x3f07c,
3737 .enable_mask = BIT(0),
3746 .halt_reg = 0x4c020,
3749 .enable_reg = 0x4c020,
3750 .enable_mask = BIT(0),
3759 .halt_reg = 0x4c024,
3762 .enable_reg = 0x4c024,
3763 .enable_mask = BIT(0),
3772 .halt_reg = 0x4c02c,
3775 .enable_reg = 0x4c02c,
3776 .enable_mask = BIT(0),
3790 .halt_reg = 0x4c01c,
3793 .enable_reg = 0x4c01c,
3794 .enable_mask = BIT(0),
3808 .halt_reg = 0x12014,
3811 .enable_reg = 0x4500c,
3821 .halt_reg = 0x12090,
3824 .enable_reg = 0x4500c,
3834 .halt_reg = 0x1203c,
3837 .enable_reg = 0x4500c,
3847 .gdscr = 0x3f078,
3860 .gdscr = 0x4c018,
3861 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3870 .gdscr = 0x4c028,
3871 .cxcs = (unsigned int []){ 0x4c02c },
3881 .gdscr = 0x4d078,
3882 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3891 .gdscr = 0x5701c,
3892 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3901 .gdscr = 0x58034,
3902 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3911 .gdscr = 0x5806c,
3912 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3921 .gdscr = 0x5901c,
3922 .clamp_io_ctrl = 0x5b00c,
3923 .cxcs = (unsigned int []){ 0x59000, 0x59024 },
3933 .gdscr = 0x5904c,
3934 .cxcs = (unsigned int []){ 0x59020 },
3943 .gdscr = 0x58078,
3944 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
4168 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
4169 [GCC_MSS_BCR] = { 0x71000 },
4170 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
4171 [GCC_USB3PHY_PHY_BCR] = { 0x3f03c },
4172 [GCC_USB3_PHY_BCR] = { 0x3f034 },
4173 [GCC_USB_30_BCR] = { 0x3f070 },
4174 [GCC_MDSS_BCR] = { 0x4d074 },
4175 [GCC_CRYPTO_BCR] = { 0x16000 },
4176 [GCC_SDCC1_BCR] = { 0x42000 },
4177 [GCC_SDCC2_BCR] = { 0x43000 },
4184 .max_register = 0x80000,