Lines Matching +full:0 +full:x5c000
74 .offset = 0x0,
77 .enable_reg = 0x4b028,
78 .enable_mask = BIT(0),
89 { 0x1, 2 },
94 .offset = 0x0,
111 .offset = 0x1000,
114 .enable_reg = 0x4b028,
126 .offset = 0x4000,
129 .enable_reg = 0x4b028,
141 .offset = 0x5000,
144 .enable_reg = 0x4b028,
156 .offset = 0x7000,
159 .enable_reg = 0x4b028,
171 .offset = 0x9000,
174 .enable_reg = 0x4b028,
186 { P_BI_TCXO, 0 },
198 { P_BI_TCXO, 0 },
212 { P_BI_TCXO, 0 },
226 { P_BI_TCXO, 0 },
236 { P_BI_TCXO, 0 },
252 { P_BI_TCXO, 0 },
260 { P_BI_TCXO, 0 },
274 { P_BI_TCXO, 0 },
288 { P_BI_TCXO, 0 },
322 { P_BI_TCXO, 0 },
338 { P_BI_TCXO, 0 },
348 { P_BI_TCXO, 0 },
364 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
374 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
384 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
394 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
404 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
414 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
424 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
434 { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 },
444 .reg = 0xa9074,
445 .shift = 0,
459 .reg = 0xa906c,
473 .reg = 0x77074,
474 .shift = 0,
488 .reg = 0x7706c,
502 .reg = 0x81060,
503 .shift = 0,
517 .reg = 0x810d0,
518 .shift = 0,
532 .reg = 0x81050,
533 .shift = 0,
547 .reg = 0x83060,
548 .shift = 0,
562 .reg = 0x830d0,
563 .shift = 0,
577 .reg = 0x83050,
578 .shift = 0,
592 .reg = 0x1b068,
593 .shift = 0,
607 .reg = 0x2f068,
608 .shift = 0,
622 F(19200000, P_BI_TCXO, 1, 0, 0),
627 .cmd_rcgr = 0xb6028,
628 .mnd_width = 0,
641 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
642 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
647 .cmd_rcgr = 0xb6060,
661 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
662 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
667 .cmd_rcgr = 0xb6048,
681 .cmd_rcgr = 0xb4028,
682 .mnd_width = 0,
695 .cmd_rcgr = 0xb4060,
709 .cmd_rcgr = 0xb4048,
723 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
724 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
729 .cmd_rcgr = 0x70004,
743 .cmd_rcgr = 0x71004,
757 .cmd_rcgr = 0x62004,
771 .cmd_rcgr = 0x1e004,
785 .cmd_rcgr = 0x1f004,
799 .cmd_rcgr = 0xa9078,
813 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
818 .cmd_rcgr = 0xa9054,
819 .mnd_width = 0,
832 .cmd_rcgr = 0x77078,
846 .cmd_rcgr = 0x77054,
847 .mnd_width = 0,
860 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
865 .cmd_rcgr = 0x3f010,
866 .mnd_width = 0,
881 F(19200000, P_BI_TCXO, 1, 0, 0),
888 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
900 .cmd_rcgr = 0x23154,
916 .cmd_rcgr = 0x23288,
927 F(19200000, P_BI_TCXO, 1, 0, 0),
934 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
946 .cmd_rcgr = 0x233bc,
962 .cmd_rcgr = 0x234f0,
978 .cmd_rcgr = 0x23624,
994 .cmd_rcgr = 0x23758,
1010 .cmd_rcgr = 0x2388c,
1026 .cmd_rcgr = 0x24154,
1042 .cmd_rcgr = 0x24288,
1058 .cmd_rcgr = 0x243bc,
1074 .cmd_rcgr = 0x244f0,
1090 .cmd_rcgr = 0x24624,
1106 .cmd_rcgr = 0x24758,
1122 .cmd_rcgr = 0x2488c,
1138 .cmd_rcgr = 0x2a154,
1154 .cmd_rcgr = 0x2a288,
1170 .cmd_rcgr = 0x2a3bc,
1186 .cmd_rcgr = 0x2a4f0,
1202 .cmd_rcgr = 0x2a624,
1218 .cmd_rcgr = 0x2a758,
1234 .cmd_rcgr = 0x2a88c,
1245 F(19200000, P_BI_TCXO, 1, 0, 0),
1250 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1253 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1254 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1266 .cmd_rcgr = 0xc4154,
1277 F(19200000, P_BI_TCXO, 1, 0, 0),
1279 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1280 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1281 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1282 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1283 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1288 .cmd_rcgr = 0x20014,
1302 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1303 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1308 .cmd_rcgr = 0x2002c,
1309 .mnd_width = 0,
1327 .cmd_rcgr = 0x21008,
1341 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1342 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1343 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1344 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1345 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1350 .cmd_rcgr = 0x8102c,
1364 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1365 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1366 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1367 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1372 .cmd_rcgr = 0x81074,
1373 .mnd_width = 0,
1386 .cmd_rcgr = 0x810a8,
1387 .mnd_width = 0,
1400 .cmd_rcgr = 0x8108c,
1401 .mnd_width = 0,
1414 .cmd_rcgr = 0x8302c,
1428 .cmd_rcgr = 0x83074,
1429 .mnd_width = 0,
1442 .cmd_rcgr = 0x830a8,
1443 .mnd_width = 0,
1456 .cmd_rcgr = 0x8308c,
1457 .mnd_width = 0,
1470 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1475 .cmd_rcgr = 0x1c028,
1489 .cmd_rcgr = 0x1c040,
1490 .mnd_width = 0,
1503 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1504 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1505 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1510 .cmd_rcgr = 0x1b028,
1524 .cmd_rcgr = 0x1b040,
1525 .mnd_width = 0,
1538 .cmd_rcgr = 0x2f028,
1552 .cmd_rcgr = 0x2f040,
1553 .mnd_width = 0,
1566 .cmd_rcgr = 0x1b06c,
1567 .mnd_width = 0,
1580 .cmd_rcgr = 0x2f06c,
1581 .mnd_width = 0,
1594 .reg = 0xa9070,
1595 .shift = 0,
1609 .reg = 0x77070,
1610 .shift = 0,
1624 .reg = 0xc4284,
1625 .shift = 0,
1639 .reg = 0x1c058,
1640 .shift = 0,
1654 .reg = 0x1b058,
1655 .shift = 0,
1669 .reg = 0x2f058,
1670 .shift = 0,
1684 .halt_reg = 0x8e200,
1686 .hwcg_reg = 0x8e200,
1689 .enable_reg = 0x4b000,
1699 .halt_reg = 0x810d4,
1701 .hwcg_reg = 0x810d4,
1704 .enable_reg = 0x810d4,
1705 .enable_mask = BIT(0),
1719 .halt_reg = 0x830d4,
1721 .hwcg_reg = 0x830d4,
1724 .enable_reg = 0x830d4,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x1c05c,
1741 .hwcg_reg = 0x1c05c,
1744 .enable_reg = 0x1c05c,
1745 .enable_mask = BIT(0),
1759 .halt_reg = 0x1b084,
1761 .hwcg_reg = 0x1b084,
1764 .enable_reg = 0x1b084,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x2f088,
1781 .hwcg_reg = 0x2f088,
1784 .enable_reg = 0x2f088,
1785 .enable_mask = BIT(0),
1799 .halt_reg = 0x76004,
1801 .hwcg_reg = 0x76004,
1804 .enable_reg = 0x76004,
1805 .enable_mask = BIT(0),
1814 .halt_reg = 0x76008,
1816 .hwcg_reg = 0x76008,
1819 .enable_reg = 0x76008,
1820 .enable_mask = BIT(0),
1829 .halt_reg = 0x7600c,
1831 .hwcg_reg = 0x7600c,
1834 .enable_reg = 0x7600c,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x44004,
1846 .hwcg_reg = 0x44004,
1849 .enable_reg = 0x4b000,
1859 .halt_reg = 0x32010,
1861 .hwcg_reg = 0x32010,
1864 .enable_reg = 0x32010,
1865 .enable_mask = BIT(0),
1874 .halt_reg = 0x32018,
1876 .hwcg_reg = 0x32018,
1879 .enable_reg = 0x32018,
1880 .enable_mask = BIT(0),
1889 .halt_reg = 0x32024,
1892 .enable_reg = 0x32024,
1893 .enable_mask = BIT(0),
1902 .halt_reg = 0x1c060,
1904 .hwcg_reg = 0x1c060,
1907 .enable_reg = 0x1c060,
1908 .enable_mask = BIT(0),
1922 .halt_reg = 0x1b088,
1924 .hwcg_reg = 0x1b088,
1927 .enable_reg = 0x1b088,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x2f084,
1944 .hwcg_reg = 0x2f084,
1947 .enable_reg = 0x2f084,
1948 .enable_mask = BIT(0),
1962 .halt_reg = 0x7d164,
1964 .hwcg_reg = 0x7d164,
1967 .enable_reg = 0x7d164,
1968 .enable_mask = BIT(0),
1977 .halt_reg = 0xc7010,
1979 .hwcg_reg = 0xc7010,
1982 .enable_reg = 0xc7010,
1983 .enable_mask = BIT(0),
1992 .halt_reg = 0x33010,
1994 .hwcg_reg = 0x33010,
1997 .enable_reg = 0x33010,
1998 .enable_mask = BIT(0),
2007 .halt_reg = 0x97448,
2010 .enable_reg = 0x97448,
2011 .enable_mask = BIT(0),
2020 .halt_reg = 0xb6018,
2022 .hwcg_reg = 0xb6018,
2025 .enable_reg = 0xb6018,
2026 .enable_mask = BIT(0),
2035 .halt_reg = 0xb6024,
2038 .enable_reg = 0xb6024,
2039 .enable_mask = BIT(0),
2053 .halt_reg = 0xb6040,
2056 .enable_reg = 0xb6040,
2057 .enable_mask = BIT(0),
2071 .halt_reg = 0xb6044,
2074 .enable_reg = 0xb6044,
2075 .enable_mask = BIT(0),
2089 .halt_reg = 0xb6020,
2091 .hwcg_reg = 0xb6020,
2094 .enable_reg = 0xb6020,
2095 .enable_mask = BIT(0),
2104 .halt_reg = 0xb4018,
2106 .hwcg_reg = 0xb4018,
2109 .enable_reg = 0xb4018,
2110 .enable_mask = BIT(0),
2119 .halt_reg = 0xb4024,
2122 .enable_reg = 0xb4024,
2123 .enable_mask = BIT(0),
2137 .halt_reg = 0xb4040,
2140 .enable_reg = 0xb4040,
2141 .enable_mask = BIT(0),
2155 .halt_reg = 0xb4044,
2158 .enable_reg = 0xb4044,
2159 .enable_mask = BIT(0),
2173 .halt_reg = 0xb4020,
2175 .hwcg_reg = 0xb4020,
2178 .enable_reg = 0xb4020,
2179 .enable_mask = BIT(0),
2188 .halt_reg = 0x70000,
2191 .enable_reg = 0x70000,
2192 .enable_mask = BIT(0),
2206 .halt_reg = 0x71000,
2209 .enable_reg = 0x71000,
2210 .enable_mask = BIT(0),
2224 .halt_reg = 0x62000,
2227 .enable_reg = 0x62000,
2228 .enable_mask = BIT(0),
2242 .halt_reg = 0x1e000,
2245 .enable_reg = 0x1e000,
2246 .enable_mask = BIT(0),
2260 .halt_reg = 0x1f000,
2263 .enable_reg = 0x1f000,
2264 .enable_mask = BIT(0),
2280 .enable_reg = 0x4b000,
2297 .enable_reg = 0x4b000,
2312 .halt_reg = 0x7d010,
2314 .hwcg_reg = 0x7d010,
2317 .enable_reg = 0x7d010,
2318 .enable_mask = BIT(0),
2327 .halt_reg = 0x7d01c,
2330 .enable_reg = 0x7d01c,
2331 .enable_mask = BIT(0),
2340 .halt_reg = 0x7d008,
2342 .hwcg_reg = 0x7d008,
2345 .enable_reg = 0x7d008,
2346 .enable_mask = BIT(0),
2355 .halt_reg = 0x7d014,
2357 .hwcg_reg = 0x7d014,
2360 .enable_reg = 0x7d014,
2361 .enable_mask = BIT(0),
2370 .halt_reg = 0xa9038,
2373 .enable_reg = 0x4b010,
2388 .halt_reg = 0xa902c,
2390 .hwcg_reg = 0xa902c,
2393 .enable_reg = 0x4b010,
2403 .halt_reg = 0xa9024,
2406 .enable_reg = 0x4b010,
2416 .halt_reg = 0xa9030,
2419 .enable_reg = 0x4b010,
2434 .halt_reg = 0xa9050,
2437 .enable_reg = 0x4b010,
2452 .halt_reg = 0xa9040,
2455 .enable_reg = 0x4b010,
2470 .halt_reg = 0xa9048,
2473 .enable_reg = 0x4b018,
2488 .halt_reg = 0xa901c,
2491 .enable_reg = 0x4b010,
2501 .halt_reg = 0xa9018,
2504 .enable_reg = 0x4b018,
2514 .halt_reg = 0x77038,
2517 .enable_reg = 0x4b000,
2532 .halt_reg = 0x7702c,
2534 .hwcg_reg = 0x7702c,
2537 .enable_reg = 0x4b008,
2547 .halt_reg = 0x77024,
2550 .enable_reg = 0x4b008,
2560 .halt_reg = 0x77030,
2563 .enable_reg = 0x4b008,
2578 .halt_reg = 0x77050,
2581 .enable_reg = 0x4b000,
2596 .halt_reg = 0x77040,
2599 .enable_reg = 0x4b008,
2614 .halt_reg = 0x77048,
2617 .enable_reg = 0x4b018,
2632 .halt_reg = 0x7701c,
2635 .enable_reg = 0x4b008,
2636 .enable_mask = BIT(0),
2645 .halt_reg = 0x77018,
2648 .enable_reg = 0x4b008,
2658 .halt_reg = 0x9746c,
2661 .enable_reg = 0x9746c,
2662 .enable_mask = BIT(0),
2671 .halt_reg = 0xb2034,
2674 .enable_reg = 0x4b020,
2684 .halt_reg = 0x3f00c,
2687 .enable_reg = 0x3f00c,
2688 .enable_mask = BIT(0),
2702 .halt_reg = 0x3f004,
2704 .hwcg_reg = 0x3f004,
2707 .enable_reg = 0x3f004,
2708 .enable_mask = BIT(0),
2717 .halt_reg = 0x3f008,
2720 .enable_reg = 0x3f008,
2721 .enable_mask = BIT(0),
2730 .halt_reg = 0x32008,
2732 .hwcg_reg = 0x32008,
2735 .enable_reg = 0x32008,
2736 .enable_mask = BIT(0),
2745 .halt_reg = 0x3200c,
2747 .hwcg_reg = 0x3200c,
2750 .enable_reg = 0x3200c,
2751 .enable_mask = BIT(0),
2760 .halt_reg = 0xc7008,
2762 .hwcg_reg = 0xc7008,
2765 .enable_reg = 0xc7008,
2766 .enable_mask = BIT(0),
2775 .halt_reg = 0xc700c,
2778 .enable_reg = 0xc700c,
2779 .enable_mask = BIT(0),
2788 .halt_reg = 0x33008,
2790 .hwcg_reg = 0x33008,
2793 .enable_reg = 0x33008,
2794 .enable_mask = BIT(0),
2803 .halt_reg = 0x3300c,
2806 .enable_reg = 0x3300c,
2807 .enable_mask = BIT(0),
2816 .halt_reg = 0x34008,
2818 .hwcg_reg = 0x34008,
2821 .enable_reg = 0x34008,
2822 .enable_mask = BIT(0),
2831 .halt_reg = 0x3400c,
2833 .hwcg_reg = 0x3400c,
2836 .enable_reg = 0x3400c,
2837 .enable_mask = BIT(0),
2846 .halt_reg = 0x34010,
2848 .hwcg_reg = 0x34010,
2851 .enable_reg = 0x34010,
2852 .enable_mask = BIT(0),
2861 .halt_reg = 0x23018,
2864 .enable_reg = 0x4b008,
2874 .halt_reg = 0x2300c,
2877 .enable_reg = 0x4b008,
2887 .halt_reg = 0x2314c,
2890 .enable_reg = 0x4b008,
2905 .halt_reg = 0x23280,
2908 .enable_reg = 0x4b008,
2923 .halt_reg = 0x233b4,
2926 .enable_reg = 0x4b008,
2941 .halt_reg = 0x234e8,
2944 .enable_reg = 0x4b008,
2959 .halt_reg = 0x2361c,
2962 .enable_reg = 0x4b008,
2977 .halt_reg = 0x23750,
2980 .enable_reg = 0x4b008,
2995 .halt_reg = 0x23884,
2998 .enable_reg = 0x4b008,
3013 .halt_reg = 0x24018,
3016 .enable_reg = 0x4b008,
3026 .halt_reg = 0x2400c,
3029 .enable_reg = 0x4b008,
3039 .halt_reg = 0x2414c,
3042 .enable_reg = 0x4b008,
3057 .halt_reg = 0x24280,
3060 .enable_reg = 0x4b008,
3075 .halt_reg = 0x243b4,
3078 .enable_reg = 0x4b008,
3093 .halt_reg = 0x244e8,
3096 .enable_reg = 0x4b008,
3111 .halt_reg = 0x2461c,
3114 .enable_reg = 0x4b008,
3129 .halt_reg = 0x24750,
3132 .enable_reg = 0x4b008,
3147 .halt_reg = 0x24884,
3150 .enable_reg = 0x4b018,
3165 .halt_reg = 0x2a018,
3168 .enable_reg = 0x4b010,
3178 .halt_reg = 0x2a00c,
3181 .enable_reg = 0x4b010,
3182 .enable_mask = BIT(0),
3191 .halt_reg = 0x2a14c,
3194 .enable_reg = 0x4b010,
3209 .halt_reg = 0x2a280,
3212 .enable_reg = 0x4b010,
3227 .halt_reg = 0x2a3b4,
3230 .enable_reg = 0x4b010,
3245 .halt_reg = 0x2a4e8,
3248 .enable_reg = 0x4b010,
3263 .halt_reg = 0x2a61c,
3266 .enable_reg = 0x4b010,
3281 .halt_reg = 0x2a750,
3284 .enable_reg = 0x4b010,
3299 .halt_reg = 0x2a884,
3302 .enable_reg = 0x4b018,
3317 .halt_reg = 0xc4018,
3320 .enable_reg = 0x4b000,
3330 .halt_reg = 0xc400c,
3333 .enable_reg = 0x4b000,
3343 .halt_reg = 0xc4280,
3346 .enable_reg = 0x4b000,
3361 .halt_reg = 0xc414c,
3364 .enable_reg = 0x4b000,
3379 .halt_reg = 0x23004,
3381 .hwcg_reg = 0x23004,
3384 .enable_reg = 0x4b008,
3394 .halt_reg = 0x23008,
3396 .hwcg_reg = 0x23008,
3399 .enable_reg = 0x4b008,
3409 .halt_reg = 0x24004,
3411 .hwcg_reg = 0x24004,
3414 .enable_reg = 0x4b008,
3424 .halt_reg = 0x24008,
3426 .hwcg_reg = 0x24008,
3429 .enable_reg = 0x4b008,
3439 .halt_reg = 0x2a004,
3441 .hwcg_reg = 0x2a004,
3444 .enable_reg = 0x4b010,
3454 .halt_reg = 0x2a008,
3456 .hwcg_reg = 0x2a008,
3459 .enable_reg = 0x4b010,
3469 .halt_reg = 0xc4004,
3471 .hwcg_reg = 0xc4004,
3474 .enable_reg = 0x4b000,
3484 .halt_reg = 0xc4008,
3486 .hwcg_reg = 0xc4008,
3489 .enable_reg = 0x4b000,
3499 .halt_reg = 0x2000c,
3502 .enable_reg = 0x2000c,
3503 .enable_mask = BIT(0),
3512 .halt_reg = 0x20004,
3515 .enable_reg = 0x20004,
3516 .enable_mask = BIT(0),
3530 .halt_reg = 0x20044,
3532 .hwcg_reg = 0x20044,
3535 .enable_reg = 0x20044,
3536 .enable_mask = BIT(0),
3550 .halt_reg = 0x9c034,
3553 .enable_reg = 0x9c034,
3554 .enable_mask = BIT(0),
3563 .halt_reg = 0x21024,
3566 .enable_reg = 0x21024,
3567 .enable_mask = BIT(0),
3576 .halt_reg = 0x21020,
3579 .enable_reg = 0x21020,
3580 .enable_mask = BIT(0),
3589 .halt_reg = 0x21004,
3592 .enable_reg = 0x21004,
3593 .enable_mask = BIT(0),
3607 .halt_reg = 0x81020,
3609 .hwcg_reg = 0x81020,
3612 .enable_reg = 0x81020,
3613 .enable_mask = BIT(0),
3622 .halt_reg = 0x81018,
3624 .hwcg_reg = 0x81018,
3627 .enable_reg = 0x81018,
3628 .enable_mask = BIT(0),
3642 .halt_reg = 0x8106c,
3644 .hwcg_reg = 0x8106c,
3647 .enable_reg = 0x8106c,
3648 .enable_mask = BIT(0),
3662 .halt_reg = 0x810a4,
3664 .hwcg_reg = 0x810a4,
3667 .enable_reg = 0x810a4,
3668 .enable_mask = BIT(0),
3682 .halt_reg = 0x81028,
3685 .enable_reg = 0x81028,
3686 .enable_mask = BIT(0),
3700 .halt_reg = 0x810c0,
3703 .enable_reg = 0x810c0,
3704 .enable_mask = BIT(0),
3718 .halt_reg = 0x81024,
3721 .enable_reg = 0x81024,
3722 .enable_mask = BIT(0),
3736 .halt_reg = 0x81064,
3738 .hwcg_reg = 0x81064,
3741 .enable_reg = 0x81064,
3742 .enable_mask = BIT(0),
3756 .halt_reg = 0x83020,
3758 .hwcg_reg = 0x83020,
3761 .enable_reg = 0x83020,
3762 .enable_mask = BIT(0),
3771 .halt_reg = 0x83018,
3773 .hwcg_reg = 0x83018,
3776 .enable_reg = 0x83018,
3777 .enable_mask = BIT(0),
3791 .halt_reg = 0x8306c,
3793 .hwcg_reg = 0x8306c,
3796 .enable_reg = 0x8306c,
3797 .enable_mask = BIT(0),
3811 .halt_reg = 0x830a4,
3813 .hwcg_reg = 0x830a4,
3816 .enable_reg = 0x830a4,
3817 .enable_mask = BIT(0),
3831 .halt_reg = 0x83028,
3834 .enable_reg = 0x83028,
3835 .enable_mask = BIT(0),
3849 .halt_reg = 0x830c0,
3852 .enable_reg = 0x830c0,
3853 .enable_mask = BIT(0),
3867 .halt_reg = 0x83024,
3870 .enable_reg = 0x83024,
3871 .enable_mask = BIT(0),
3885 .halt_reg = 0x83064,
3887 .hwcg_reg = 0x83064,
3890 .enable_reg = 0x83064,
3891 .enable_mask = BIT(0),
3905 .halt_reg = 0x1c018,
3908 .enable_reg = 0x1c018,
3909 .enable_mask = BIT(0),
3923 .halt_reg = 0x1c024,
3926 .enable_reg = 0x1c024,
3927 .enable_mask = BIT(0),
3941 .halt_reg = 0x1c020,
3944 .enable_reg = 0x1c020,
3945 .enable_mask = BIT(0),
3954 .halt_reg = 0x1b018,
3957 .enable_reg = 0x1b018,
3958 .enable_mask = BIT(0),
3972 .halt_reg = 0x1b024,
3975 .enable_reg = 0x1b024,
3976 .enable_mask = BIT(0),
3990 .halt_reg = 0x1b020,
3993 .enable_reg = 0x1b020,
3994 .enable_mask = BIT(0),
4003 .halt_reg = 0x2f018,
4006 .enable_reg = 0x2f018,
4007 .enable_mask = BIT(0),
4021 .halt_reg = 0x2f024,
4024 .enable_reg = 0x2f024,
4025 .enable_mask = BIT(0),
4039 .halt_reg = 0x2f020,
4042 .enable_reg = 0x2f020,
4043 .enable_mask = BIT(0),
4052 .halt_reg = 0x1b05c,
4055 .enable_reg = 0x1b05c,
4056 .enable_mask = BIT(0),
4070 .halt_reg = 0x1b060,
4073 .enable_reg = 0x1b060,
4074 .enable_mask = BIT(0),
4088 .halt_reg = 0x1b064,
4090 .hwcg_reg = 0x1b064,
4093 .enable_reg = 0x1b064,
4094 .enable_mask = BIT(0),
4108 .halt_reg = 0x2f05c,
4111 .enable_reg = 0x2f05c,
4112 .enable_mask = BIT(0),
4126 .halt_reg = 0x2f060,
4129 .enable_reg = 0x2f060,
4130 .enable_mask = BIT(0),
4144 .halt_reg = 0x2f064,
4147 .enable_reg = 0x2f064,
4148 .enable_mask = BIT(0),
4162 .halt_reg = 0x97468,
4165 .enable_reg = 0x97468,
4166 .enable_mask = BIT(0),
4175 .halt_reg = 0x34014,
4177 .hwcg_reg = 0x34014,
4180 .enable_reg = 0x34014,
4181 .enable_mask = BIT(0),
4190 .halt_reg = 0x3401c,
4192 .hwcg_reg = 0x3401c,
4195 .enable_reg = 0x3401c,
4196 .enable_mask = BIT(0),
4205 .gdscr = 0xa9004,
4206 .collapse_ctrl = 0x4b104,
4207 .collapse_mask = BIT(0),
4208 .en_rest_wait_val = 0x2,
4209 .en_few_wait_val = 0x2,
4210 .clk_dis_wait_val = 0xf,
4219 .gdscr = 0x77004,
4220 .collapse_ctrl = 0x4b104,
4222 .en_rest_wait_val = 0x2,
4223 .en_few_wait_val = 0x2,
4224 .clk_dis_wait_val = 0xf,
4233 .gdscr = 0x81004,
4234 .en_rest_wait_val = 0x2,
4235 .en_few_wait_val = 0x2,
4236 .clk_dis_wait_val = 0xf,
4245 .gdscr = 0x83004,
4246 .en_rest_wait_val = 0x2,
4247 .en_few_wait_val = 0x2,
4248 .clk_dis_wait_val = 0xf,
4257 .gdscr = 0x1c004,
4258 .en_rest_wait_val = 0x2,
4259 .en_few_wait_val = 0x2,
4260 .clk_dis_wait_val = 0xf,
4269 .gdscr = 0x1b004,
4270 .en_rest_wait_val = 0x2,
4271 .en_few_wait_val = 0x2,
4272 .clk_dis_wait_val = 0xf,
4281 .gdscr = 0x2f004,
4282 .en_rest_wait_val = 0x2,
4283 .en_few_wait_val = 0x2,
4284 .clk_dis_wait_val = 0xf,
4293 .gdscr = 0xb6004,
4294 .en_rest_wait_val = 0x2,
4295 .en_few_wait_val = 0x2,
4296 .clk_dis_wait_val = 0xf,
4305 .gdscr = 0xb4004,
4306 .en_rest_wait_val = 0x2,
4307 .en_few_wait_val = 0x2,
4308 .clk_dis_wait_val = 0xf,
4555 [GCC_CAMERA_BCR] = { 0x32000 },
4556 [GCC_DISPLAY1_BCR] = { 0xc7000 },
4557 [GCC_DISPLAY_BCR] = { 0x33000 },
4558 [GCC_EMAC0_BCR] = { 0xb6000 },
4559 [GCC_EMAC1_BCR] = { 0xb4000 },
4560 [GCC_GPU_BCR] = { 0x7d000 },
4561 [GCC_MMSS_BCR] = { 0x17000 },
4562 [GCC_PCIE_0_BCR] = { 0xa9000 },
4563 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
4564 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
4565 [GCC_PCIE_0_PHY_BCR] = { 0xad144 },
4566 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
4567 [GCC_PCIE_1_BCR] = { 0x77000 },
4568 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
4569 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
4570 [GCC_PCIE_1_PHY_BCR] = { 0xae08c },
4571 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
4572 [GCC_PDM_BCR] = { 0x3f000 },
4573 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
4574 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
4575 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 },
4576 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 },
4577 [GCC_SDCC1_BCR] = { 0x20000 },
4578 [GCC_TSCSS_BCR] = { 0x21000 },
4579 [GCC_UFS_CARD_BCR] = { 0x81000 },
4580 [GCC_UFS_PHY_BCR] = { 0x83000 },
4581 [GCC_USB20_PRIM_BCR] = { 0x1c000 },
4582 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 },
4583 [GCC_USB2_PHY_SEC_BCR] = { 0x5c02c },
4584 [GCC_USB30_PRIM_BCR] = { 0x1b000 },
4585 [GCC_USB30_SEC_BCR] = { 0x2f000 },
4586 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
4587 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 },
4588 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
4589 [GCC_USB3_PHY_SEC_BCR] = { 0x5c00c },
4590 [GCC_USB3_PHY_TERT_BCR] = { 0x5c030 },
4591 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 },
4592 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c },
4593 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
4594 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 },
4595 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
4596 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
4597 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
4598 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
4599 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
4600 [GCC_VIDEO_BCR] = { 0x34000 },
4644 .max_register = 0xc7018,
4679 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ in gcc_sa8775p_probe()
4680 qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ in gcc_sa8775p_probe()
4681 qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ in gcc_sa8775p_probe()
4682 qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ in gcc_sa8775p_probe()
4683 qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ in gcc_sa8775p_probe()
4684 qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ in gcc_sa8775p_probe()
4685 qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sa8775p_probe()
4686 qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ in gcc_sa8775p_probe()
4687 qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ in gcc_sa8775p_probe()