Searched +full:0 +full:x5000000 (Results 1 – 22 of 22) sorted by relevance
/linux-6.12.1/Documentation/devicetree/bindings/phy/ |
D | ti,phy-j721e-wiz.yaml | 61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 90 const: 0 113 "^pll[0|1]-refclk$": 126 const: 0 157 const: 0 166 "^serdes@[0-9a-f]+$": 210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 214 ranges = <0x5000000 0x5000000 0x10000>; 218 #clock-cells = <0>; 224 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/marvell/ |
D | armada-385-linksys-rango.dts | 20 wan_amber@0 { 22 reg = <0x0>; 27 reg = <0x1>; 32 reg = <0x5>; 37 reg = <0x6>; 42 reg = <0x7>; 47 reg = <0x8>; 52 reg = <0x9>; 89 partition@0 { 91 reg = <0x0000000 0x200000>; /* 2MiB */ [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
D | hisi504-nand.txt | 31 reg = <0x4020000 0x10000>, <0x5000000 0x1000>; 32 interrupts = <0 379 4>; 40 partition@0 { 42 reg = <0x00000000 0x00400000>;
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/linux-6.12.1/include/linux/mfd/ |
D | cs40l50.h | 20 #define CS40L50_BLOCK_ENABLES2 0x201C 21 #define CS40L50_ERR_RLS 0x2034 22 #define CS40L50_BST_LPMODE_SEL 0x3810 23 #define CS40L50_DCM_LOW_POWER 0x1 24 #define CS40L50_OVERTEMP_WARN 0x4000010 27 #define CS40L50_IRQ1_INT_1 0xE010 29 #define CS40L50_IRQ1_INT_2 0xE014 30 #define CS40L50_IRQ1_INT_8 0xE02C 31 #define CS40L50_IRQ1_INT_9 0xE030 32 #define CS40L50_IRQ1_INT_10 0xE034 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/ |
D | ti,k3-m4f-rproc.yaml | 92 reg = <0x00 0x9cb00000 0x00 0x100000>; 98 reg = <0x00 0x9cc00000 0x00 0xe00000>; 107 mailbox0_cluster0: mailbox-0 { 113 reg = <0x00 0x5000000 0x00 0x30000>, 114 <0x00 0x5040000 0x00 0x10000>; 123 ti,sci-proc-ids = <0x18 0xff>;
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/linux-6.12.1/arch/arm/boot/dts/cirrus/ |
D | ep93xx-edb9302.dts | 17 memory@0 { 20 reg = <0x0000000 0x800000>, 21 <0x1000000 0x800000>, 22 <0x4000000 0x800000>, 23 <0x5000000 0x800000>; 34 led-0 { 36 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 56 reg = <0x60000000 0x1000000>; 66 gpio-ranges = <&syscon 0 153 1>, 77 gpio-ranges = <&syscon 0 143 1>, [all …]
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/linux-6.12.1/arch/arm64/boot/dts/qcom/ |
D | msm8916-gplus-fl8005a.dts | 36 ocv-capacity-table-0 = 46 <3310000 1>, <3000000 0>; 55 pinctrl-0 = <&camera_flash_default>; 68 pinctrl-0 = <&gpio_keys_default>; 81 pinctrl-0 = <&gpio_leds_default>; 102 pinctrl-0 = <&usb_id_default>; 113 reg = <0x38>; 128 pinctrl-0 = <&touchscreen_default>; 138 reg = <0x0 0x86800000 0x0 0x5000000>; 174 pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
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D | msm8916-longcheer-l8910.dts | 34 pinctrl-0 = <&spk_ext_pa_default>; 43 pinctrl-0 = <&camera_front_flash_default>; 57 pinctrl-0 = <&gpio_keys_default>; 71 led-0 { 78 pinctrl-0 = <&button_backlight_default>; 86 pinctrl-0 = <&usb_id_default>; 95 reg = <0x30>; 97 #size-cells = <0>; 102 pinctrl-0 = <&status_led_default>; 110 #size-cells = <0>; [all …]
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D | msm8916-longcheer-l8150.dts | 30 * It must be loaded at 0x8b600000. Unfortunately, this also means that 31 * mpss_mem does not fit when loaded to the typical address at 0x86800000. 35 * boot when placed at 0x8a800000 to 0x8e800000. 42 reg = <0x0 0x8b600000 0x0 0x600000>; 47 reg = <0x0 0x8e800000 0x0 0x5000000>; 60 ocv-capacity-table-0 = <4330000 100>, <4265000 95>, 68 <3000000 0>; 75 pinctrl-0 = <&gpio_keys_default>; 97 pinctrl-0 = <&ctp_pwr_en_default>; 106 pinctrl-0 = <&camera_flash_default>; [all …]
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D | msm8916-samsung-fortuna-common.dtsi | 25 reg = <0x0 0x85a00000 0x0 0x600000>; 38 pwms = <&clk_pwm 0 100000>; 42 brightness-levels = <0 255>; 46 pinctrl-0 = <&backlight_en_default>; 56 pinctrl-0 = <&backlight_pwm_default>; 63 pinctrl-0 = <&gpio_keys_default>; 90 sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 93 pinctrl-0 = <&nfc_i2c_default>; 97 #size-cells = <0>; 101 reg = <0x27>; [all …]
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D | msm8916-alcatel-idol347.dts | 33 reg = <0x0 0x86680000 0x0 0x160000>; 44 pinctrl-0 = <&gpio_keys_default>; 59 pinctrl-0 = <&gpio_leds_default>; 61 led-0 { 75 pinctrl-0 = <&headphones_avdd_default>; 83 pinctrl-0 = <&usb_id_default>; 92 reg = <0x10>; 96 pinctrl-0 = <&headphones_pdn_default>; 98 #sound-dai-cells = <0>; 103 reg = <0x34>; [all …]
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D | sm8450.dtsi | 39 #clock-cells = <0>; 45 #clock-cells = <0>; 52 #size-cells = <0>; 54 CPU0: cpu@0 { 57 reg = <0x0 0x0>; 62 qcom,freq-domain = <&cpufreq_hw 0>; 64 clocks = <&cpufreq_hw 0>; 81 reg = <0x0 0x100>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 88 clocks = <&cpufreq_hw 0>; [all …]
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/linux-6.12.1/drivers/misc/mei/ |
D | hw-me-regs.h | 12 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */ 13 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */ 14 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */ 15 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */ 17 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */ 18 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */ 20 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */ 21 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */ 22 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */ 23 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */ [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/display/msm/ |
D | gpu.yaml | 32 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' 44 - pattern: '^amd,imageon-200\.[0-1]$' 149 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' 225 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' 252 reg = <0xfdb00000 0x10000>; 266 iommus = <&gpu_iommu 0>; 273 reg = <0xfdd00000 0x2000>, 274 <0xfec00000 0x180000>; 283 ranges = <0 0xfec00000 0x100000>; [all …]
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/linux-6.12.1/arch/riscv/boot/dts/allwinner/ |
D | sunxi-d1s-t113.dtsi | 21 #clock-cells = <0>; 39 reg = <0x2000000 0x800>; 150 reg = <0x2001000 0x1000>; 161 reg = <0x2009000 0x400>; 172 reg = <0x2031000 0x400>; 181 #sound-dai-cells = <0>; 187 reg = <0x2033000 0x1000>; 196 #sound-dai-cells = <0>; 202 reg = <0x2034000 0x1000>; 211 #sound-dai-cells = <0>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ |
D | k3-j721e-main.dtsi | 15 #clock-cells = <0>; 17 clock-frequency = <0>; 21 #clock-cells = <0>; 23 clock-frequency = <0>; 30 reg = <0x0 0x70000000 0x0 0x800000>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 45 ranges = <0x0 0x0 0x00100000 0x1c000>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1088a.dtsi | 27 #size-cells = <0>; 30 cpu0: cpu@0 { 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 reg = <0x1>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 51 reg = <0x2>; 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 60 reg = <0x3>; 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>; [all …]
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D | fsl-ls208xa.dtsi | 33 #size-cells = <0>; 38 reg = <0x00000000 0x80000000 0 0x80000000>; 44 #clock-cells = <0>; 51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 67 reg = <0x0 0x6020000 0 0x20000>; 73 reg = <0x0 0x1e60000 0x0 0x4>; [all …]
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D | fsl-ls1028a.dtsi | 23 #size-cells = <0>; 25 cpu0: cpu@0 { 28 reg = <0x0>; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 i-cache-size = <0xc000>; 34 d-cache-size = <0x8000>; 45 reg = <0x1>; 47 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 48 i-cache-size = <0xc000>; 51 d-cache-size = <0x8000>; [all …]
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D | fsl-lx2160a.dtsi | 12 /memreserve/ 0x80000000 0x00010000; 26 #size-cells = <0>; 29 cpu0: cpu@0 { 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 38 i-cache-size = <0xC000>; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_d.h | 27 #define mmMM_INDEX 0x0 28 #define mmMM_INDEX_HI 0x6 29 #define mmMM_DATA 0x1 30 #define mmBIF_MM_INDACCESS_CNTL 0x1500 31 #define mmBUS_CNTL 0x1508 32 #define mmCONFIG_CNTL 0x1509 33 #define mmCONFIG_MEMSIZE 0x150a 34 #define mmCONFIG_F0_BASE 0x150b 35 #define mmCONFIG_APER_SIZE 0x150c 36 #define mmCONFIG_REG_APER_SIZE 0x150d [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | vega10_hwmgr.c | 56 #define smnPCIE_LC_SPEED_CNTL 0x11140290 57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 63 …DF_CS_AON0_DramBaseAddress0 0x0044 64 …ne mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 67 …AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 68 …AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 69 …AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 70 …AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 71 …AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc [all …]
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