Lines Matching +full:0 +full:x5000000
61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
90 const: 0
113 "^pll[0|1]-refclk$":
126 const: 0
157 const: 0
166 "^serdes@[0-9a-f]+$":
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
214 ranges = <0x5000000 0x5000000 0x10000>;
218 #clock-cells = <0>;
224 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
225 #clock-cells = <0>;
227 assigned-clock-parents = <&k3_clks 293 0>;
232 #clock-cells = <0>;
237 #clock-cells = <0>;
241 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
243 #clock-cells = <0>;
251 reg = <0x5000000 0x10000>;
253 #size-cells = <0>;
254 resets = <&serdes_wiz0 0>;