Lines Matching +full:0 +full:x5000000
56 #define smnPCIE_LC_SPEED_CNTL 0x11140290
57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
63 …DF_CS_AON0_DramBaseAddress0 0x0044
64 …ne mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
67 …AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
68 …AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
69 …AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
70 …AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
71 …AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
72 …mBaseAddress0__AddrRngVal_MASK 0x00000001L
73 …mBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
74 …mBaseAddress0__IntLvNumChan_MASK 0x000000F0L
75 …mBaseAddress0__IntLvAddrSel_MASK 0x00000700L
76 …mBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
79 CLK_SMNCLK = 0,
146 data->registry_data.disable_water_mark = 0; in vega10_set_default_registry_data()
164 data->registry_data.db_ramping_support = 0; in vega10_set_default_registry_data()
165 data->registry_data.td_ramping_support = 0; in vega10_set_default_registry_data()
166 data->registry_data.tcp_ramping_support = 0; in vega10_set_default_registry_data()
167 data->registry_data.dbr_ramping_support = 0; in vega10_set_default_registry_data()
169 data->registry_data.gc_didt_support = 0; in vega10_set_default_registry_data()
170 data->registry_data.psm_didt_support = 0; in vega10_set_default_registry_data()
300 return 0; in vega10_set_features_platform_caps()
313 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; in vega10_odn_initial_default_setting()
326 for (i = 0; i < vddc_lookup_table->count; i++) in vega10_odn_initial_default_setting()
331 dep_table[0] = table_info->vdd_dep_on_sclk; in vega10_odn_initial_default_setting()
334 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; in vega10_odn_initial_default_setting()
338 for (i = 0; i < 3; i++) in vega10_odn_initial_default_setting()
341 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) in vega10_odn_initial_default_setting()
342 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; in vega10_odn_initial_default_setting()
343 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) in vega10_odn_initial_default_setting()
344 odn_table->min_vddc = dep_table[0]->entries[0].vddc; in vega10_odn_initial_default_setting()
354 return 0; in vega10_odn_initial_default_setting()
367 for (i = 0; i < GNLD_FEATURES_MAX; i++) { in vega10_init_dpm_defaults()
368 data->smu_features[i].smu_feature_id = 0xffff; in vega10_init_dpm_defaults()
495 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) in vega10_init_dpm_defaults()
503 if ((hwmgr->chip_id == 0x6862 || in vega10_init_dpm_defaults()
504 hwmgr->chip_id == 0x6861 || in vega10_init_dpm_defaults()
505 hwmgr->chip_id == 0x6868) && in vega10_init_dpm_defaults()
506 (hw_revision == 0) && in vega10_init_dpm_defaults()
507 (sub_vendor_id != 0x1002)) in vega10_init_dpm_defaults()
520 return 0; in vega10_init_dpm_defaults()
533 PP_ASSERT_WITH_CODE(lookup_table->count != 0, in vega10_get_socclk_for_voltage_evv()
537 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ in vega10_get_socclk_for_voltage_evv()
538 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { in vega10_get_socclk_for_voltage_evv()
550 return 0; in vega10_get_socclk_for_voltage_evv()
553 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
558 * return: always 0.
564 uint32_t vddc = 0; in vega10_get_evv_voltages()
566 uint32_t sclk = 0; in vega10_get_evv_voltages()
573 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { in vega10_get_evv_voltages()
581 socclk_table->entries[j].cks_enable == 0) { in vega10_get_evv_voltages()
595 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), in vega10_get_evv_voltages()
599 if (vddc != 0 && vddc != vv_id) { in vega10_get_evv_voltages()
607 return 0; in vega10_get_evv_voltages()
622 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ in vega10_patch_with_vdd_leakage()
623 for (index = 0; index < leakage_table->count; index++) { in vega10_patch_with_vdd_leakage()
642 * return: always 0
650 for (i = 0; i < lookup_table->count; i++) in vega10_patch_lookup_table_with_leakage()
654 return 0; in vega10_patch_lookup_table_with_leakage()
663 return 0; in vega10_patch_clock_voltage_limits_with_vddc_leakage()
679 for (i = 0; i < 6; i++) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
682 case 0: vdt = table_info->vdd_dep_on_socclk; break; in vega10_patch_voltage_dependency_tables_with_lookup_table()
690 for (entry_id = 0; entry_id < vdt->count; entry_id++) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
697 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
703 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
716 return 0; in vega10_patch_voltage_dependency_tables_with_lookup_table()
731 for (i = 0; i < table_size - 1; i++) { in vega10_sort_lookup_table()
732 for (j = i + 1; j > 0; j--) { in vega10_sort_lookup_table()
741 return 0; in vega10_sort_lookup_table()
746 int result = 0; in vega10_complete_dependency_tables()
812 return 0; in vega10_set_private_data_based_on_pptable()
823 return 0; in vega10_hwmgr_backend_fini()
828 int result = 0; in vega10_hwmgr_backend_init()
830 uint32_t config_telemetry = 0; in vega10_hwmgr_backend_init()
845 data->disable_dpm_mask = 0xff; in vega10_hwmgr_backend_init()
858 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | in vega10_hwmgr_backend_init()
859 (vol_table.telemetry_offset & 0xff); in vega10_hwmgr_backend_init()
877 ((vol_table.telemetry_slope << 24) & 0xff000000) | in vega10_hwmgr_backend_init()
878 ((vol_table.telemetry_offset << 16) & 0xff0000); in vega10_hwmgr_backend_init()
920 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ in vega10_hwmgr_backend_init()
943 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()
957 data->low_sclk_interrupt_threshold = 0; in vega10_init_sclk_threshold()
959 return 0; in vega10_init_sclk_threshold()
969 uint32_t mask = 0; in vega10_setup_dpm_led_config()
971 int32_t ret = 0; in vega10_setup_dpm_led_config()
978 for (i = 0, j = 0; i < 32; i++) { in vega10_setup_dpm_led_config()
988 pp_table->LedPin0 = (uint8_t)(mask & 0xff); in vega10_setup_dpm_led_config()
989 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); in vega10_setup_dpm_led_config()
990 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); in vega10_setup_dpm_led_config()
991 return 0; in vega10_setup_dpm_led_config()
997 return 0; in vega10_setup_asic_task()
1009 0, in vega10_setup_asic_task()
1012 return 0; in vega10_setup_asic_task()
1020 * return: 0 in success
1041 for (i = 0; i < vol_table->count; i++) { in vega10_trim_voltage_table()
1045 for (j = 0; j < table->count; j++) { in vega10_trim_voltage_table()
1063 return 0; in vega10_trim_voltage_table()
1076 vol_table->mask_low = 0; in vega10_get_mvdd_voltage_table()
1077 vol_table->phase_delay = 0; in vega10_get_mvdd_voltage_table()
1080 for (i = 0; i < vol_table->count; i++) { in vega10_get_mvdd_voltage_table()
1082 vol_table->entries[i].smio_low = 0; in vega10_get_mvdd_voltage_table()
1090 return 0; in vega10_get_mvdd_voltage_table()
1103 vol_table->mask_low = 0; in vega10_get_vddci_voltage_table()
1104 vol_table->phase_delay = 0; in vega10_get_vddci_voltage_table()
1107 for (i = 0; i < dep_table->count; i++) { in vega10_get_vddci_voltage_table()
1109 vol_table->entries[i].smio_low = 0; in vega10_get_vddci_voltage_table()
1116 return 0; in vega10_get_vddci_voltage_table()
1129 vol_table->mask_low = 0; in vega10_get_vdd_voltage_table()
1130 vol_table->phase_delay = 0; in vega10_get_vdd_voltage_table()
1133 for (i = 0; i < vol_table->count; i++) { in vega10_get_vdd_voltage_table()
1135 vol_table->entries[i].smio_low = 0; in vega10_get_vdd_voltage_table()
1138 return 0; in vega10_get_vdd_voltage_table()
1158 for (i = 0; i < max_vol_steps; i++) in vega10_trim_voltage_table_to_fit_state_table()
1168 * return: always 0
1222 return 0; in vega10_construct_voltage_tables()
1227 * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1234 dpm_state->soft_min_level = 0xff; in vega10_init_dpm_state()
1235 dpm_state->soft_max_level = 0xff; in vega10_init_dpm_state()
1236 dpm_state->hard_min_level = 0xff; in vega10_init_dpm_state()
1237 dpm_state->hard_max_level = 0xff; in vega10_init_dpm_state()
1246 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1248 for (i = 0; i < dep_table->count; i++) { in vega10_setup_default_single_dpm_table()
1249 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1272 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_setup_default_pcie_table()
1296 return 0; in vega10_setup_default_pcie_table()
1365 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()
1371 data->dpm_table.mem_table.count = 0; in vega10_setup_default_dpm_tables()
1376 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) in vega10_setup_default_dpm_tables()
1381 data->dpm_table.eclk_table.count = 0; in vega10_setup_default_dpm_tables()
1383 for (i = 0; i < dep_mm_table->count; i++) { in vega10_setup_default_dpm_tables()
1384 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1389 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; in vega10_setup_default_dpm_tables()
1395 data->dpm_table.vclk_table.count = 0; in vega10_setup_default_dpm_tables()
1396 data->dpm_table.dclk_table.count = 0; in vega10_setup_default_dpm_tables()
1398 for (i = 0; i < dep_mm_table->count; i++) { in vega10_setup_default_dpm_tables()
1399 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1404 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; in vega10_setup_default_dpm_tables()
1411 for (i = 0; i < dep_mm_table->count; i++) { in vega10_setup_default_dpm_tables()
1412 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1417 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; in vega10_setup_default_dpm_tables()
1458 data->custom_profile_mode[0] = 0; in vega10_setup_default_dpm_tables()
1459 data->custom_profile_mode[1] = 0; in vega10_setup_default_dpm_tables()
1460 data->custom_profile_mode[2] = 0; in vega10_setup_default_dpm_tables()
1461 data->custom_profile_mode[3] = 0; in vega10_setup_default_dpm_tables()
1467 return 0; in vega10_setup_default_dpm_tables()
1475 * return: Always 0.
1497 return 0; in vega10_populate_ulv_state()
1514 return 0; in vega10_populate_single_lclk_level()
1522 uint32_t pcie_gen = 0, pcie_width = 0; in vega10_override_pcie_parameters()
1533 pcie_gen = 0; in vega10_override_pcie_parameters()
1548 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1557 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1563 return 0; in vega10_override_pcie_parameters()
1575 for (i = 0; i < pcie_table->count; i++) { in vega10_populate_smc_link_levels()
1624 uint32_t i = 0; in vega10_populate_single_gfx_level()
1639 for (i = 0; i < dep_on_sclk->count; i++) { in vega10_populate_single_gfx_level()
1654 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ in vega10_populate_single_gfx_level()
1657 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ in vega10_populate_single_gfx_level()
1667 return 0; in vega10_populate_single_gfx_level()
1678 * return: 0 on success
1694 for (i = 0; i < dep_on_soc->count; i++) { in vega10_populate_single_soc_level()
1700 for (i = 0; i < dep_on_soc->count; i++) { in vega10_populate_single_soc_level()
1718 return 0; in vega10_populate_single_soc_level()
1734 int result = 0; in vega10_populate_all_graphic_levels()
1737 for (i = 0; i < dpm_table->count; i++) { in vega10_populate_all_graphic_levels()
1761 for (i = 0; i < dpm_table->count; i++) { in vega10_populate_all_graphic_levels()
1791 uint8_t soc_vid = 0; in vega10_populate_vddc_soc_levels()
1800 for (i = 0; i < max_vddc_level; i++) { in vega10_populate_vddc_soc_levels()
1815 * return: 0 on success..
1828 uint32_t i = 0; in vega10_populate_single_memory_level()
1843 for (i = 0; i < dep_on_mclk->count; i++) { in vega10_populate_single_memory_level()
1868 return 0; in vega10_populate_single_memory_level()
1884 int result = 0; in vega10_populate_all_memory_levels()
1887 for (i = 0; i < dpm_table->count; i++) { in vega10_populate_all_memory_levels()
1930 uint16_t clk = 0, vddc = 0; in vega10_populate_single_display_type()
1931 uint8_t vid = 0; in vega10_populate_single_display_type()
1954 for (i = 0; i < dep_table->count; i++) { in vega10_populate_single_display_type()
1973 return 0; in vega10_populate_single_display_type()
1980 for (i = 0; i < DSPCLK_COUNT; i++) { in vega10_populate_all_display_clock_levels()
1986 return 0; in vega10_populate_all_display_clock_levels()
2008 for (i = 0; i < dep_table->count; i++) { in vega10_populate_single_eclock_level()
2013 return 0; in vega10_populate_single_eclock_level()
2024 for (i = 0; i < dpm_table->count; i++) { in vega10_populate_smc_vce_levels()
2060 return 0; in vega10_populate_single_vclock_level()
2076 return 0; in vega10_populate_single_dclock_level()
2094 for (i = 0; i < vclk_dpm_table->count; i++) { in vega10_populate_smc_uvd_levels()
2112 for (i = 0; i < dclk_dpm_table->count; i++) { in vega10_populate_smc_uvd_levels()
2130 for (i = 0; i < dep_table->count; i++) { in vega10_populate_smc_uvd_levels()
2147 return 0; in vega10_populate_smc_uvd_levels()
2160 for (i = 0; i < dep_table->count; i++) { in vega10_populate_clock_stretcher_table()
2166 return 0; in vega10_populate_clock_stretcher_table()
2177 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; in vega10_populate_avfs_parameters()
2178 int result = 0; in vega10_populate_avfs_parameters()
2181 pp_table->MinVoltageVid = (uint8_t)0xff; in vega10_populate_avfs_parameters()
2182 pp_table->MaxVoltageVid = (uint8_t)0; in vega10_populate_avfs_parameters()
2192 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); in vega10_populate_avfs_parameters()
2229 pp_table->AvfsGbCksOn.b_shift = 0; in vega10_populate_avfs_parameters()
2241 pp_table->AvfsGbCksOff.b_shift = 0; in vega10_populate_avfs_parameters()
2243 for (i = 0; i < dep_table->count; i++) in vega10_populate_avfs_parameters()
2350 pp_table->AcgAvfsGb.b_shift = 0; in vega10_populate_avfs_parameters()
2357 return 0; in vega10_populate_avfs_parameters()
2367 if (0 == vega10_enable_smc_features(hwmgr, true, in vega10_acg_enable()
2377 agc_btc_response = 0; in vega10_acg_enable()
2384 if (0 == vega10_enable_smc_features(hwmgr, true, in vega10_acg_enable()
2393 return 0; in vega10_acg_enable()
2406 return 0; in vega10_acg_disable()
2413 struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; in vega10_populate_gpio_parameters()
2425 pp_table->VR0HotGpio = 0; in vega10_populate_gpio_parameters()
2426 pp_table->VR0HotPolarity = 0; in vega10_populate_gpio_parameters()
2427 pp_table->VR1HotGpio = 0; in vega10_populate_gpio_parameters()
2428 pp_table->VR1HotPolarity = 0; in vega10_populate_gpio_parameters()
2436 pp_table->AcDcGpio = 0; in vega10_populate_gpio_parameters()
2437 pp_table->AcDcPolarity = 0; in vega10_populate_gpio_parameters()
2451 return 0; in vega10_avfs_enable()
2470 return 0; in vega10_avfs_enable()
2486 return 0; in vega10_update_avfs()
2491 int result = 0; in vega10_populate_and_upload_avfs_fuse_override()
2493 uint64_t serial_number = 0; in vega10_populate_and_upload_avfs_fuse_override()
2508 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { in vega10_populate_and_upload_avfs_fuse_override()
2540 for (i = 0; i < dep_table->count; i++) { in vega10_check_dpm_table_updated()
2549 for (i = 0; i < dep_table->count; i++) { in vega10_check_dpm_table_updated()
2561 * return: always 0
2580 return 0; in vega10_init_smc_table()
2678 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); in vega10_init_smc_table()
2681 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); in vega10_init_smc_table()
2685 if (0 != boot_up_values.usVddc) { in vega10_init_smc_table()
2731 return 0; in vega10_init_smc_table()
2751 return 0; in vega10_enable_thermal_protection()
2771 return 0; in vega10_disable_thermal_protection()
2799 return 0; in vega10_enable_vrhot_feature()
2814 return 0; in vega10_enable_ulv()
2829 return 0; in vega10_disable_ulv()
2868 return 0; in vega10_enable_deep_sleep_master_switch()
2907 return 0; in vega10_disable_deep_sleep_master_switch()
2913 uint32_t i, feature_mask = 0; in vega10_stop_dpm()
2916 return 0; in vega10_stop_dpm()
2925 for (i = 0; i < GNLD_DPM_MAX; i++) { in vega10_stop_dpm()
2945 * return: 0 on at least one DPM is successfully enabled.
2950 uint32_t i, feature_mask = 0; in vega10_start_dpm()
2952 for (i = 0; i < GNLD_DPM_MAX; i++) { in vega10_start_dpm()
2966 for (i = 0; i < GNLD_DPM_MAX; i++) { in vega10_start_dpm()
2982 PPSMC_MSG_SetFloorSocVoltage, 0, in vega10_start_dpm()
3005 return 0; in vega10_start_dpm()
3023 return 0; in vega10_enable_disable_PCC_limit_feature()
3036 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; in vega10_populate_umdpstate_clocks()
3037 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; in vega10_populate_umdpstate_clocks()
3053 int tmp_result, result = 0; in vega10_enable_dpm_tasks()
3175 ATOM_Vega10_DISALLOW_ON_DC) != 0); in vega10_get_pp_table_entry_callback_func()
3181 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); in vega10_get_pp_table_entry_callback_func()
3183 power_state->validation.supportedPowerLevels = 0; in vega10_get_pp_table_entry_callback_func()
3184 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3185 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3186 power_state->temperatures.min = 0; in vega10_get_pp_table_entry_callback_func()
3187 power_state->temperatures.max = 0; in vega10_get_pp_table_entry_callback_func()
3217 if (gfxclk_dep_table->ucRevId == 0) { in vega10_get_pp_table_entry_callback_func()
3221 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) in vega10_get_pp_table_entry_callback_func()
3229 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) in vega10_get_pp_table_entry_callback_func()
3238 return 0; in vega10_get_pp_table_entry_callback_func()
3267 return 0; in vega10_get_pp_table_entry()
3273 return 0; in vega10_patch_boot_state()
3284 struct PP_Clocks minimum_clocks = {0}; in vega10_apply_state_adjust_rules()
3296 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; in vega10_apply_state_adjust_rules()
3315 for (i = 0; i < vega10_ps->performance_level_count; i++) { in vega10_apply_state_adjust_rules()
3345 count >= 0; count--) { in vega10_apply_state_adjust_rules()
3354 if (count < 0) in vega10_apply_state_adjust_rules()
3355 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; in vega10_apply_state_adjust_rules()
3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3378 sclk = vega10_ps->performance_levels[0].gfx_clock; in vega10_apply_state_adjust_rules()
3379 mclk = vega10_ps->performance_levels[0].mem_clock; in vega10_apply_state_adjust_rules()
3389 vega10_ps->performance_levels[0].gfx_clock = sclk; in vega10_apply_state_adjust_rules()
3390 vega10_ps->performance_levels[0].mem_clock = mclk; in vega10_apply_state_adjust_rules()
3393 vega10_ps->performance_levels[0].gfx_clock) in vega10_apply_state_adjust_rules()
3394 vega10_ps->performance_levels[0].gfx_clock = in vega10_apply_state_adjust_rules()
3398 /* Set Mclk the max of level 0 and level 1 */ in vega10_apply_state_adjust_rules()
3406 for (i = 0; i < data->mclk_latency_table.count; i++) { in vega10_apply_state_adjust_rules()
3409 vega10_ps->performance_levels[0].mem_clock) && in vega10_apply_state_adjust_rules()
3414 vega10_ps->performance_levels[0].mem_clock = mclk; in vega10_apply_state_adjust_rules()
3417 vega10_ps->performance_levels[0].mem_clock) in vega10_apply_state_adjust_rules()
3418 vega10_ps->performance_levels[0].mem_clock = in vega10_apply_state_adjust_rules()
3423 for (i = 0; i < vega10_ps->performance_level_count; i++) { in vega10_apply_state_adjust_rules()
3429 return 0; in vega10_apply_state_adjust_rules()
3451 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3463 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3478 return 0; in vega10_find_dpm_states_clocks_in_dpm_table()
3484 int result = 0; in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3492 return 0; in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3495 for (count = 0; count < dpm_table->gfx_table.count; count++) in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3501 for (count = 0; count < dpm_table->mem_table.count; count++) in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3508 PP_ASSERT_WITH_CODE((0 == result), in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3516 PP_ASSERT_WITH_CODE((0 == result), in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3532 for (i = 0; i < dpm_table->count; i++) { in vega10_trim_single_dpm_states()
3539 return 0; in vega10_trim_single_dpm_states()
3549 for (i = 0; i < dpm_table->count; i++) { in vega10_trim_single_dpm_states_with_mask()
3558 return 0; in vega10_trim_single_dpm_states_with_mask()
3571 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; in vega10_trim_dpm_states()
3575 vega10_ps->performance_levels[0].soc_clock, in vega10_trim_dpm_states()
3580 vega10_ps->performance_levels[0].gfx_clock, in vega10_trim_dpm_states()
3586 vega10_ps->performance_levels[0].mem_clock, in vega10_trim_dpm_states()
3589 return 0; in vega10_trim_dpm_states()
3597 for (i = 0; i < table->count; i++) { in vega10_find_lowest_dpm_level()
3608 uint32_t i = 0; in vega10_find_highest_dpm_level()
3611 for (i = table->count; i > 0; i--) { in vega10_find_highest_dpm_level()
3682 return 0; in vega10_upload_dpm_bootup_level()
3696 return 0; in vega10_upload_dpm_bootup_level()
3730 return 0; in vega10_upload_dpm_max_level()
3744 return 0; in vega10_upload_dpm_max_level()
3793 return 0; in vega10_generate_dpm_level_enable_mask()
3809 return 0; in vega10_enable_disable_vce_dpm()
3815 uint32_t low_sclk_interrupt_threshold = 0; in vega10_update_sclk_threshold()
3818 (data->low_sclk_interrupt_threshold != 0)) { in vega10_update_sclk_threshold()
3832 return 0; in vega10_update_sclk_threshold()
3838 int tmp_result, result = 0; in vega10_set_power_state_tasks()
3881 return 0; in vega10_set_power_state_tasks()
3900 return vega10_ps->performance_levels[0].gfx_clock; in vega10_dpm_get_sclk()
3922 return vega10_ps->performance_levels[0].mem_clock; in vega10_dpm_get_mclk()
3944 return 0; in vega10_get_gpu_power()
3951 uint32_t sclk_mhz, mclk_idx, activity_percent = 0; in vega10_read_sensor()
3954 int ret = 0; in vega10_read_sensor()
3977 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, in vega10_read_sensor()
3999 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; in vega10_read_sensor()
4003 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; in vega10_read_sensor()
4010 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & in vega10_read_sensor()
4014 return 0; in vega10_read_sensor()
4033 has_disp ? 1 : 0, in vega10_notify_smc_display_change()
4040 int result = 0; in vega10_display_clock_voltage_request()
4043 DSPCLK_e clk_select = 0; in vega10_display_clock_voltage_request()
4044 uint32_t clk_request = 0; in vega10_display_clock_voltage_request()
4083 if (mclk_table == NULL || mclk_table->count == 0) in vega10_get_uclk_index()
4084 return 0; in vega10_get_uclk_index()
4088 for(i = 0; i < count; i++) { in vega10_get_uclk_index()
4106 struct PP_Clocks min_clocks = {0}; in vega10_notify_smc_display_config_after_ps_adjustment()
4121 for (i = 0; i < dpm_table->count; i++) { in vega10_notify_smc_display_config_after_ps_adjustment()
4141 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()
4148 return 0; in vega10_notify_smc_display_config_after_ps_adjustment()
4170 return 0; in vega10_force_dpm_highest()
4192 return 0; in vega10_force_dpm_lowest()
4216 return 0; in vega10_unforce_dpm_levels()
4234 *sclk_mask = 0; in vega10_get_profiling_clk_mask()
4236 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4249 return 0; in vega10_get_profiling_clk_mask()
4281 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; in vega10_force_clock_level()
4282 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; in vega10_force_clock_level()
4294 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; in vega10_force_clock_level()
4295 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; in vega10_force_clock_level()
4308 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; in vega10_force_clock_level()
4309 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; in vega10_force_clock_level()
4330 return 0; in vega10_force_clock_level()
4336 int ret = 0; in vega10_dpm_force_dpm_level()
4337 uint32_t sclk_mask = 0; in vega10_dpm_force_dpm_level()
4338 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level()
4339 uint32_t soc_mask = 0; in vega10_dpm_force_dpm_level()
4401 return 0; in vega10_get_dal_power_level()
4413 clocks->num_levels = 0; in vega10_get_sclks()
4414 for (i = 0; i < dep_table->count; i++) { in vega10_get_sclks()
4432 uint32_t j = 0; in vega10_get_memclocks()
4435 for (i = 0; i < dep_table->count; i++) { in vega10_get_memclocks()
4459 for (i = 0; i < dep_table->count; i++) { in vega10_get_dcefclocks()
4461 clocks->data[i].latency_in_us = 0; in vega10_get_dcefclocks()
4475 for (i = 0; i < dep_table->count; i++) { in vega10_get_socclocks()
4477 clocks->data[i].latency_in_us = 0; in vega10_get_socclocks()
4503 return 0; in vega10_get_clock_by_type_with_latency()
4535 for (i = 0; i < dep_table->count; i++) { in vega10_get_clock_by_type_with_voltage()
4545 return 0; in vega10_get_clock_by_type_with_voltage()
4560 return 0; in vega10_set_watermarks_for_clocks_ranges()
4602 int ret = 0; in vega10_get_ppfeature_status()
4603 int size = 0; in vega10_get_ppfeature_status()
4612 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); in vega10_get_ppfeature_status()
4614 output_title[0], in vega10_get_ppfeature_status()
4617 for (i = 0; i < GNLD_FEATURES_MAX; i++) { in vega10_get_ppfeature_status()
4618 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", in vega10_get_ppfeature_status()
4632 int ret = 0; in vega10_set_ppfeature_status()
4646 pr_debug("features_to_disable 0x%llx\n", features_to_disable); in vega10_set_ppfeature_status()
4647 pr_debug("features_to_enable 0x%llx\n", features_to_enable); in vega10_set_ppfeature_status()
4661 return 0; in vega10_set_ppfeature_status()
4694 uint32_t i, now, count = 0; in vega10_emit_clock_levels()
4695 int ret = 0; in vega10_emit_clock_levels()
4703 if (unlikely(ret != 0)) in vega10_emit_clock_levels()
4711 for (i = 0; i < count; i++) in vega10_emit_clock_levels()
4721 if (unlikely(ret != 0)) in vega10_emit_clock_levels()
4724 for (i = 0; i < mclk_table->count; i++) in vega10_emit_clock_levels()
4734 if (unlikely(ret != 0)) in vega10_emit_clock_levels()
4737 for (i = 0; i < soc_table->count; i++) in vega10_emit_clock_levels()
4749 if (unlikely(ret != 0)) in vega10_emit_clock_levels()
4752 for (i = 0; i < dcef_table->count; i++) in vega10_emit_clock_levels()
4763 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_emit_clock_levels()
4768 (gen_speed == 0) ? "2.5GT/s," : in vega10_emit_clock_levels()
4790 for (i = 0; i < podn_vdd_dep->count; i++) in vega10_emit_clock_levels()
4801 for (i = 0; i < podn_vdd_dep->count; i++) in vega10_emit_clock_levels()
4812 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, in vega10_emit_clock_levels()
4815 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, in vega10_emit_clock_levels()
4840 int i, ret, now, size = 0, count = 0; in vega10_print_clock_levels()
4856 for (i = 0; i < count; i++) in vega10_print_clock_levels()
4869 for (i = 0; i < mclk_table->count; i++) in vega10_print_clock_levels()
4882 for (i = 0; i < soc_table->count; i++) in vega10_print_clock_levels()
4896 for (i = 0; i < dcef_table->count; i++) in vega10_print_clock_levels()
4907 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_print_clock_levels()
4912 (gen_speed == 0) ? "2.5GT/s," : in vega10_print_clock_levels()
4932 for (i = 0; i < podn_vdd_dep->count; i++) in vega10_print_clock_levels()
4942 for (i = 0; i < podn_vdd_dep->count; i++) in vega10_print_clock_levels()
4952 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, in vega10_print_clock_levels()
4955 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, in vega10_print_clock_levels()
4972 int result = 0; in vega10_display_configuration_changed_task()
5002 return 0; in vega10_enable_disable_uvd_dpm()
5051 return 0; in vega10_check_states_equal()
5054 for (i = 0; i < vega10_psa->performance_level_count; i++) { in vega10_check_states_equal()
5061 return 0; in vega10_check_states_equal()
5072 return 0; in vega10_check_states_equal()
5094 int tmp_result, result = 0; in vega10_disable_dpm_tasks()
5097 return 0; in vega10_disable_dpm_tasks()
5103 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5107 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5111 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5115 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5119 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5123 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5127 PP_ASSERT_WITH_CODE((tmp_result == 0), in vega10_disable_dpm_tasks()
5140 PP_ASSERT_WITH_CODE((0 == result), in vega10_power_off_asic()
5198 return 0; in vega10_set_sclk_od()
5252 return 0; in vega10_set_mclk_od()
5284 return 0; in vega10_notify_cac_buffer_info()
5296 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); in vega10_get_thermal_temperature_range()
5318 return 0; in vega10_get_thermal_temperature_range()
5324 uint32_t i, size = 0; in vega10_get_power_profile_mode()
5325 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, in vega10_get_power_profile_mode()
5327 {90, 60, 0, 0,}, in vega10_get_power_profile_mode()
5328 {70, 60, 0, 0,}, in vega10_get_power_profile_mode()
5329 {70, 90, 0, 0,}, in vega10_get_power_profile_mode()
5330 {30, 60, 0, 6,}, in vega10_get_power_profile_mode()
5344 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], in vega10_get_power_profile_mode()
5347 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) in vega10_get_power_profile_mode()
5350 profile_mode_setting[i][0], profile_mode_setting[i][1], in vega10_get_power_profile_mode()
5355 data->custom_profile_mode[0], data->custom_profile_mode[1], in vega10_get_power_profile_mode()
5364 return (adev->pdev->device == 0x6860); in vega10_get_power_profile_mode_quirks()
5377 if (size != 0 && size != 4) in vega10_set_power_profile_mode()
5380 /* If size = 0 and the CUSTOM profile has been set already in vega10_set_power_profile_mode()
5384 if (size == 0) { in vega10_set_power_profile_mode()
5385 if (data->custom_profile_mode[0] != 0) in vega10_set_power_profile_mode()
5391 data->custom_profile_mode[0] = busy_set_point = input[0]; in vega10_set_power_profile_mode()
5409 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), in vega10_set_power_profile_mode()
5414 return 0; in vega10_set_power_profile_mode()
5434 if (golden_table->dpm_levels[0].value > clk || in vega10_check_clk_voltage_valid()
5437 golden_table->dpm_levels[0].value/100, in vega10_check_clk_voltage_valid()
5443 if (golden_table->dpm_levels[0].value > clk || in vega10_check_clk_voltage_valid()
5446 golden_table->dpm_levels[0].value/100, in vega10_check_clk_voltage_valid()
5537 for (i = 0; i < podn_vdd_dep->count; i++) in vega10_odn_update_soc_table()
5541 for (i = 0; i < dpm_table->count; i++) { in vega10_odn_update_soc_table()
5542 for (j = 0; j < od_vddc_lookup_table->count; j++) { in vega10_odn_update_soc_table()
5556 for (i = 0; i < dep_table->count; i++) { in vega10_odn_update_soc_table()
5628 return 0; in vega10_odn_edit_dpm_table()
5631 return 0; in vega10_odn_edit_dpm_table()
5636 for (i = 0; i < size; i += 3) { in vega10_odn_edit_dpm_table()
5639 return 0; in vega10_odn_edit_dpm_table()
5654 return 0; in vega10_odn_edit_dpm_table()
5671 return 0; in vega10_set_mp1_state()
5674 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, in vega10_set_mp1_state()
5678 return 0; in vega10_set_mp1_state()
5701 return 0; in vega10_get_performance_level()
5707 uint32_t feature_mask = 0; in vega10_disable_power_features_for_compute_performance()
5711 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5713 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5715 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5717 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5719 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5722 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5724 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5726 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5728 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5730 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; in vega10_disable_power_features_for_compute_performance()
5753 return 0; in vega10_disable_power_features_for_compute_performance()
5838 return 0; in vega10_hwmgr_init()