1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 can0_pins: can0-pins { 57 pins = "PB2", "PB3"; 58 function = "can0"; 59 }; 60 61 /omit-if-no-ref/ 62 can1_pins: can1-pins { 63 pins = "PB4", "PB5"; 64 function = "can1"; 65 }; 66 67 /omit-if-no-ref/ 68 clk_pg11_pin: clk-pg11-pin { 69 pins = "PG11"; 70 function = "clk"; 71 }; 72 73 /omit-if-no-ref/ 74 dsi_4lane_pins: dsi-4lane-pins { 75 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 76 "PD6", "PD7", "PD8", "PD9"; 77 drive-strength = <30>; 78 function = "dsi"; 79 }; 80 81 /omit-if-no-ref/ 82 lcd_rgb666_pins: lcd-rgb666-pins { 83 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 84 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 85 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 86 "PD18", "PD19", "PD20", "PD21"; 87 function = "lcd0"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc0_pins: mmc0-pins { 92 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 93 function = "mmc0"; 94 }; 95 96 /omit-if-no-ref/ 97 mmc1_pins: mmc1-pins { 98 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 99 function = "mmc1"; 100 }; 101 102 /omit-if-no-ref/ 103 mmc2_pins: mmc2-pins { 104 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 105 function = "mmc2"; 106 }; 107 108 /omit-if-no-ref/ 109 rgmii_pe_pins: rgmii-pe-pins { 110 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 111 "PE5", "PE6", "PE7", "PE8", "PE9", 112 "PE11", "PE12", "PE13", "PE14", "PE15"; 113 function = "emac"; 114 }; 115 116 /omit-if-no-ref/ 117 rmii_pe_pins: rmii-pe-pins { 118 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 119 "PE5", "PE6", "PE7", "PE8", "PE9"; 120 function = "emac"; 121 }; 122 123 /omit-if-no-ref/ 124 spi0_pins: spi0-pins { 125 pins = "PC2", "PC3", "PC4", "PC5"; 126 function = "spi0"; 127 }; 128 129 /omit-if-no-ref/ 130 uart1_pg6_pins: uart1-pg6-pins { 131 pins = "PG6", "PG7"; 132 function = "uart1"; 133 }; 134 135 /omit-if-no-ref/ 136 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 137 pins = "PG8", "PG9"; 138 function = "uart1"; 139 }; 140 141 /omit-if-no-ref/ 142 uart3_pb_pins: uart3-pb-pins { 143 pins = "PB6", "PB7"; 144 function = "uart3"; 145 }; 146 }; 147 148 ccu: clock-controller@2001000 { 149 compatible = "allwinner,sun20i-d1-ccu"; 150 reg = <0x2001000 0x1000>; 151 clocks = <&dcxo>, 152 <&rtc CLK_OSC32K>, 153 <&rtc CLK_IOSC>; 154 clock-names = "hosc", "losc", "iosc"; 155 #clock-cells = <1>; 156 #reset-cells = <1>; 157 }; 158 159 gpadc: adc@2009000 { 160 compatible = "allwinner,sun20i-d1-gpadc"; 161 reg = <0x2009000 0x400>; 162 clocks = <&ccu CLK_BUS_GPADC>; 163 resets = <&ccu RST_BUS_GPADC>; 164 interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; 165 status = "disabled"; 166 #io-channel-cells = <1>; 167 }; 168 169 dmic: dmic@2031000 { 170 compatible = "allwinner,sun20i-d1-dmic", 171 "allwinner,sun50i-h6-dmic"; 172 reg = <0x2031000 0x400>; 173 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&ccu CLK_BUS_DMIC>, 175 <&ccu CLK_DMIC>; 176 clock-names = "bus", "mod"; 177 resets = <&ccu RST_BUS_DMIC>; 178 dmas = <&dma 8>; 179 dma-names = "rx"; 180 status = "disabled"; 181 #sound-dai-cells = <0>; 182 }; 183 184 i2s1: i2s@2033000 { 185 compatible = "allwinner,sun20i-d1-i2s", 186 "allwinner,sun50i-r329-i2s"; 187 reg = <0x2033000 0x1000>; 188 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&ccu CLK_BUS_I2S1>, 190 <&ccu CLK_I2S1>; 191 clock-names = "apb", "mod"; 192 resets = <&ccu RST_BUS_I2S1>; 193 dmas = <&dma 4>, <&dma 4>; 194 dma-names = "rx", "tx"; 195 status = "disabled"; 196 #sound-dai-cells = <0>; 197 }; 198 199 i2s2: i2s@2034000 { 200 compatible = "allwinner,sun20i-d1-i2s", 201 "allwinner,sun50i-r329-i2s"; 202 reg = <0x2034000 0x1000>; 203 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&ccu CLK_BUS_I2S2>, 205 <&ccu CLK_I2S2>; 206 clock-names = "apb", "mod"; 207 resets = <&ccu RST_BUS_I2S2>; 208 dmas = <&dma 5>, <&dma 5>; 209 dma-names = "rx", "tx"; 210 status = "disabled"; 211 #sound-dai-cells = <0>; 212 }; 213 214 timer: timer@2050000 { 215 compatible = "allwinner,sun20i-d1-timer", 216 "allwinner,sun8i-a23-timer"; 217 reg = <0x2050000 0xa0>; 218 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 219 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&dcxo>; 221 }; 222 223 wdt: watchdog@20500a0 { 224 compatible = "allwinner,sun20i-d1-wdt-reset", 225 "allwinner,sun20i-d1-wdt"; 226 reg = <0x20500a0 0x20>; 227 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 229 clock-names = "hosc", "losc"; 230 status = "reserved"; 231 }; 232 233 uart0: serial@2500000 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x2500000 0x400>; 236 reg-io-width = <4>; 237 reg-shift = <2>; 238 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&ccu CLK_BUS_UART0>; 240 resets = <&ccu RST_BUS_UART0>; 241 dmas = <&dma 14>, <&dma 14>; 242 dma-names = "tx", "rx"; 243 status = "disabled"; 244 }; 245 246 uart1: serial@2500400 { 247 compatible = "snps,dw-apb-uart"; 248 reg = <0x2500400 0x400>; 249 reg-io-width = <4>; 250 reg-shift = <2>; 251 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&ccu CLK_BUS_UART1>; 253 resets = <&ccu RST_BUS_UART1>; 254 dmas = <&dma 15>, <&dma 15>; 255 dma-names = "tx", "rx"; 256 status = "disabled"; 257 }; 258 259 uart2: serial@2500800 { 260 compatible = "snps,dw-apb-uart"; 261 reg = <0x2500800 0x400>; 262 reg-io-width = <4>; 263 reg-shift = <2>; 264 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&ccu CLK_BUS_UART2>; 266 resets = <&ccu RST_BUS_UART2>; 267 dmas = <&dma 16>, <&dma 16>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 uart3: serial@2500c00 { 273 compatible = "snps,dw-apb-uart"; 274 reg = <0x2500c00 0x400>; 275 reg-io-width = <4>; 276 reg-shift = <2>; 277 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&ccu CLK_BUS_UART3>; 279 resets = <&ccu RST_BUS_UART3>; 280 dmas = <&dma 17>, <&dma 17>; 281 dma-names = "tx", "rx"; 282 status = "disabled"; 283 }; 284 285 uart4: serial@2501000 { 286 compatible = "snps,dw-apb-uart"; 287 reg = <0x2501000 0x400>; 288 reg-io-width = <4>; 289 reg-shift = <2>; 290 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&ccu CLK_BUS_UART4>; 292 resets = <&ccu RST_BUS_UART4>; 293 dmas = <&dma 18>, <&dma 18>; 294 dma-names = "tx", "rx"; 295 status = "disabled"; 296 }; 297 298 uart5: serial@2501400 { 299 compatible = "snps,dw-apb-uart"; 300 reg = <0x2501400 0x400>; 301 reg-io-width = <4>; 302 reg-shift = <2>; 303 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&ccu CLK_BUS_UART5>; 305 resets = <&ccu RST_BUS_UART5>; 306 dmas = <&dma 19>, <&dma 19>; 307 dma-names = "tx", "rx"; 308 status = "disabled"; 309 }; 310 311 i2c0: i2c@2502000 { 312 compatible = "allwinner,sun20i-d1-i2c", 313 "allwinner,sun8i-v536-i2c", 314 "allwinner,sun6i-a31-i2c"; 315 reg = <0x2502000 0x400>; 316 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&ccu CLK_BUS_I2C0>; 318 resets = <&ccu RST_BUS_I2C0>; 319 dmas = <&dma 43>, <&dma 43>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 326 i2c1: i2c@2502400 { 327 compatible = "allwinner,sun20i-d1-i2c", 328 "allwinner,sun8i-v536-i2c", 329 "allwinner,sun6i-a31-i2c"; 330 reg = <0x2502400 0x400>; 331 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ccu CLK_BUS_I2C1>; 333 resets = <&ccu RST_BUS_I2C1>; 334 dmas = <&dma 44>, <&dma 44>; 335 dma-names = "rx", "tx"; 336 status = "disabled"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 }; 340 341 i2c2: i2c@2502800 { 342 compatible = "allwinner,sun20i-d1-i2c", 343 "allwinner,sun8i-v536-i2c", 344 "allwinner,sun6i-a31-i2c"; 345 reg = <0x2502800 0x400>; 346 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&ccu CLK_BUS_I2C2>; 348 resets = <&ccu RST_BUS_I2C2>; 349 dmas = <&dma 45>, <&dma 45>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 356 i2c3: i2c@2502c00 { 357 compatible = "allwinner,sun20i-d1-i2c", 358 "allwinner,sun8i-v536-i2c", 359 "allwinner,sun6i-a31-i2c"; 360 reg = <0x2502c00 0x400>; 361 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&ccu CLK_BUS_I2C3>; 363 resets = <&ccu RST_BUS_I2C3>; 364 dmas = <&dma 46>, <&dma 46>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 }; 370 371 can0: can@2504000 { 372 compatible = "allwinner,sun20i-d1-can"; 373 reg = <0x02504000 0x400>; 374 interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&ccu CLK_BUS_CAN0>; 376 resets = <&ccu RST_BUS_CAN0>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&can0_pins>; 379 status = "disabled"; 380 }; 381 382 can1: can@2504400 { 383 compatible = "allwinner,sun20i-d1-can"; 384 reg = <0x02504400 0x400>; 385 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&ccu CLK_BUS_CAN1>; 387 resets = <&ccu RST_BUS_CAN1>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&can1_pins>; 390 status = "disabled"; 391 }; 392 393 syscon: syscon@3000000 { 394 compatible = "allwinner,sun20i-d1-system-control"; 395 reg = <0x3000000 0x1000>; 396 ranges; 397 #address-cells = <1>; 398 #size-cells = <1>; 399 400 regulators@3000150 { 401 compatible = "allwinner,sun20i-d1-system-ldos"; 402 reg = <0x3000150 0x4>; 403 404 reg_ldoa: ldoa { 405 }; 406 407 reg_ldob: ldob { 408 }; 409 }; 410 }; 411 412 dma: dma-controller@3002000 { 413 compatible = "allwinner,sun20i-d1-dma"; 414 reg = <0x3002000 0x1000>; 415 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 417 clock-names = "bus", "mbus"; 418 resets = <&ccu RST_BUS_DMA>; 419 dma-channels = <16>; 420 dma-requests = <48>; 421 #dma-cells = <1>; 422 }; 423 424 sid: efuse@3006000 { 425 compatible = "allwinner,sun20i-d1-sid"; 426 reg = <0x3006000 0x1000>; 427 #address-cells = <1>; 428 #size-cells = <1>; 429 }; 430 431 crypto: crypto@3040000 { 432 compatible = "allwinner,sun20i-d1-crypto"; 433 reg = <0x3040000 0x800>; 434 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&ccu CLK_BUS_CE>, 436 <&ccu CLK_CE>, 437 <&ccu CLK_MBUS_CE>, 438 <&rtc CLK_IOSC>; 439 clock-names = "bus", "mod", "ram", "trng"; 440 resets = <&ccu RST_BUS_CE>; 441 }; 442 443 mbus: dram-controller@3102000 { 444 compatible = "allwinner,sun20i-d1-mbus"; 445 reg = <0x3102000 0x1000>, 446 <0x3103000 0x1000>; 447 reg-names = "mbus", "dram"; 448 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_MBUS>, 450 <&ccu CLK_DRAM>, 451 <&ccu CLK_BUS_DRAM>; 452 clock-names = "mbus", "dram", "bus"; 453 dma-ranges = <0 0x40000000 0x80000000>; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 #interconnect-cells = <1>; 457 }; 458 459 mmc0: mmc@4020000 { 460 compatible = "allwinner,sun20i-d1-mmc"; 461 reg = <0x4020000 0x1000>; 462 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 464 clock-names = "ahb", "mmc"; 465 resets = <&ccu RST_BUS_MMC0>; 466 reset-names = "ahb"; 467 cap-sd-highspeed; 468 max-frequency = <150000000>; 469 no-mmc; 470 status = "disabled"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 }; 474 475 mmc1: mmc@4021000 { 476 compatible = "allwinner,sun20i-d1-mmc"; 477 reg = <0x4021000 0x1000>; 478 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 480 clock-names = "ahb", "mmc"; 481 resets = <&ccu RST_BUS_MMC1>; 482 reset-names = "ahb"; 483 cap-sd-highspeed; 484 max-frequency = <150000000>; 485 no-mmc; 486 status = "disabled"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 491 mmc2: mmc@4022000 { 492 compatible = "allwinner,sun20i-d1-emmc", 493 "allwinner,sun50i-a100-emmc"; 494 reg = <0x4022000 0x1000>; 495 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 497 clock-names = "ahb", "mmc"; 498 resets = <&ccu RST_BUS_MMC2>; 499 reset-names = "ahb"; 500 cap-mmc-highspeed; 501 max-frequency = <150000000>; 502 mmc-ddr-1_8v; 503 mmc-ddr-3_3v; 504 no-sd; 505 no-sdio; 506 status = "disabled"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 }; 510 511 spi0: spi@4025000 { 512 compatible = "allwinner,sun20i-d1-spi", 513 "allwinner,sun50i-r329-spi"; 514 reg = <0x04025000 0x1000>; 515 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 517 clock-names = "ahb", "mod"; 518 dmas = <&dma 22>, <&dma 22>; 519 dma-names = "rx", "tx"; 520 resets = <&ccu RST_BUS_SPI0>; 521 status = "disabled"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 }; 525 526 spi1: spi@4026000 { 527 compatible = "allwinner,sun20i-d1-spi-dbi", 528 "allwinner,sun50i-r329-spi-dbi", 529 "allwinner,sun50i-r329-spi"; 530 reg = <0x04026000 0x1000>; 531 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 533 clock-names = "ahb", "mod"; 534 dmas = <&dma 23>, <&dma 23>; 535 dma-names = "rx", "tx"; 536 resets = <&ccu RST_BUS_SPI1>; 537 status = "disabled"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 }; 541 542 usb_otg: usb@4100000 { 543 compatible = "allwinner,sun20i-d1-musb", 544 "allwinner,sun8i-a33-musb"; 545 reg = <0x4100000 0x400>; 546 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "mc"; 548 clocks = <&ccu CLK_BUS_OTG>; 549 resets = <&ccu RST_BUS_OTG>; 550 extcon = <&usbphy 0>; 551 phys = <&usbphy 0>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 usbphy: phy@4100400 { 557 compatible = "allwinner,sun20i-d1-usb-phy"; 558 reg = <0x4100400 0x100>, 559 <0x4101800 0x100>, 560 <0x4200800 0x100>; 561 reg-names = "phy_ctrl", 562 "pmu0", 563 "pmu1"; 564 clocks = <&dcxo>, 565 <&dcxo>; 566 clock-names = "usb0_phy", 567 "usb1_phy"; 568 resets = <&ccu RST_USB_PHY0>, 569 <&ccu RST_USB_PHY1>; 570 reset-names = "usb0_reset", 571 "usb1_reset"; 572 status = "disabled"; 573 #phy-cells = <1>; 574 }; 575 576 ehci0: usb@4101000 { 577 compatible = "allwinner,sun20i-d1-ehci", 578 "generic-ehci"; 579 reg = <0x4101000 0x100>; 580 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&ccu CLK_BUS_OHCI0>, 582 <&ccu CLK_BUS_EHCI0>, 583 <&ccu CLK_USB_OHCI0>; 584 resets = <&ccu RST_BUS_OHCI0>, 585 <&ccu RST_BUS_EHCI0>; 586 phys = <&usbphy 0>; 587 phy-names = "usb"; 588 status = "disabled"; 589 }; 590 591 ohci0: usb@4101400 { 592 compatible = "allwinner,sun20i-d1-ohci", 593 "generic-ohci"; 594 reg = <0x4101400 0x100>; 595 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&ccu CLK_BUS_OHCI0>, 597 <&ccu CLK_USB_OHCI0>; 598 resets = <&ccu RST_BUS_OHCI0>; 599 phys = <&usbphy 0>; 600 phy-names = "usb"; 601 status = "disabled"; 602 }; 603 604 ehci1: usb@4200000 { 605 compatible = "allwinner,sun20i-d1-ehci", 606 "generic-ehci"; 607 reg = <0x4200000 0x100>; 608 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&ccu CLK_BUS_OHCI1>, 610 <&ccu CLK_BUS_EHCI1>, 611 <&ccu CLK_USB_OHCI1>; 612 resets = <&ccu RST_BUS_OHCI1>, 613 <&ccu RST_BUS_EHCI1>; 614 phys = <&usbphy 1>; 615 phy-names = "usb"; 616 status = "disabled"; 617 }; 618 619 ohci1: usb@4200400 { 620 compatible = "allwinner,sun20i-d1-ohci", 621 "generic-ohci"; 622 reg = <0x4200400 0x100>; 623 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&ccu CLK_BUS_OHCI1>, 625 <&ccu CLK_USB_OHCI1>; 626 resets = <&ccu RST_BUS_OHCI1>; 627 phys = <&usbphy 1>; 628 phy-names = "usb"; 629 status = "disabled"; 630 }; 631 632 emac: ethernet@4500000 { 633 compatible = "allwinner,sun20i-d1-emac", 634 "allwinner,sun50i-a64-emac"; 635 reg = <0x4500000 0x10000>; 636 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 637 interrupt-names = "macirq"; 638 clocks = <&ccu CLK_BUS_EMAC>; 639 clock-names = "stmmaceth"; 640 resets = <&ccu RST_BUS_EMAC>; 641 reset-names = "stmmaceth"; 642 syscon = <&syscon>; 643 status = "disabled"; 644 645 mdio: mdio { 646 compatible = "snps,dwmac-mdio"; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 }; 650 }; 651 652 display_clocks: clock-controller@5000000 { 653 compatible = "allwinner,sun20i-d1-de2-clk", 654 "allwinner,sun50i-h5-de2-clk"; 655 reg = <0x5000000 0x10000>; 656 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 657 clock-names = "bus", "mod"; 658 resets = <&ccu RST_BUS_DE>; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 }; 662 663 mixer0: mixer@5100000 { 664 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 665 reg = <0x5100000 0x100000>; 666 clocks = <&display_clocks CLK_BUS_MIXER0>, 667 <&display_clocks CLK_MIXER0>; 668 clock-names = "bus", "mod"; 669 resets = <&display_clocks RST_MIXER0>; 670 671 ports { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 675 mixer0_out: port@1 { 676 reg = <1>; 677 678 mixer0_out_tcon_top_mixer0: endpoint { 679 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 680 }; 681 }; 682 }; 683 }; 684 685 mixer1: mixer@5200000 { 686 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 687 reg = <0x5200000 0x100000>; 688 clocks = <&display_clocks CLK_BUS_MIXER1>, 689 <&display_clocks CLK_MIXER1>; 690 clock-names = "bus", "mod"; 691 resets = <&display_clocks RST_MIXER1>; 692 693 ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 mixer1_out: port@1 { 698 reg = <1>; 699 700 mixer1_out_tcon_top_mixer1: endpoint { 701 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 702 }; 703 }; 704 }; 705 }; 706 707 dsi: dsi@5450000 { 708 compatible = "allwinner,sun20i-d1-mipi-dsi", 709 "allwinner,sun50i-a100-mipi-dsi"; 710 reg = <0x5450000 0x1000>; 711 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&ccu CLK_BUS_MIPI_DSI>, 713 <&tcon_top CLK_TCON_TOP_DSI>; 714 clock-names = "bus", "mod"; 715 resets = <&ccu RST_BUS_MIPI_DSI>; 716 phys = <&dphy>; 717 phy-names = "dphy"; 718 status = "disabled"; 719 720 port { 721 dsi_in_tcon_lcd0: endpoint { 722 remote-endpoint = <&tcon_lcd0_out_dsi>; 723 }; 724 }; 725 }; 726 727 dphy: phy@5451000 { 728 compatible = "allwinner,sun20i-d1-mipi-dphy", 729 "allwinner,sun50i-a100-mipi-dphy"; 730 reg = <0x5451000 0x1000>; 731 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&ccu CLK_BUS_MIPI_DSI>, 733 <&ccu CLK_MIPI_DSI>; 734 clock-names = "bus", "mod"; 735 resets = <&ccu RST_BUS_MIPI_DSI>; 736 #phy-cells = <0>; 737 }; 738 739 tcon_top: tcon-top@5460000 { 740 compatible = "allwinner,sun20i-d1-tcon-top"; 741 reg = <0x5460000 0x1000>; 742 clocks = <&ccu CLK_BUS_DPSS_TOP>, 743 <&ccu CLK_TCON_TV>, 744 <&ccu CLK_TVE>, 745 <&ccu CLK_TCON_LCD0>; 746 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 747 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 748 resets = <&ccu RST_BUS_DPSS_TOP>; 749 #clock-cells = <1>; 750 751 ports { 752 #address-cells = <1>; 753 #size-cells = <0>; 754 755 tcon_top_mixer0_in: port@0 { 756 reg = <0>; 757 758 tcon_top_mixer0_in_mixer0: endpoint { 759 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 760 }; 761 }; 762 763 tcon_top_mixer0_out: port@1 { 764 reg = <1>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 769 reg = <0>; 770 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 771 }; 772 773 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 774 reg = <2>; 775 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 776 }; 777 }; 778 779 tcon_top_mixer1_in: port@2 { 780 reg = <2>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 784 tcon_top_mixer1_in_mixer1: endpoint@1 { 785 reg = <1>; 786 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 787 }; 788 }; 789 790 tcon_top_mixer1_out: port@3 { 791 reg = <3>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 795 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 796 reg = <0>; 797 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 798 }; 799 800 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 801 reg = <2>; 802 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 803 }; 804 }; 805 806 tcon_top_hdmi_in: port@4 { 807 reg = <4>; 808 809 tcon_top_hdmi_in_tcon_tv0: endpoint { 810 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 811 }; 812 }; 813 814 tcon_top_hdmi_out: port@5 { 815 reg = <5>; 816 }; 817 }; 818 }; 819 820 tcon_lcd0: lcd-controller@5461000 { 821 compatible = "allwinner,sun20i-d1-tcon-lcd"; 822 reg = <0x5461000 0x1000>; 823 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&ccu CLK_BUS_TCON_LCD0>, 825 <&ccu CLK_TCON_LCD0>; 826 clock-names = "ahb", "tcon-ch0"; 827 clock-output-names = "tcon-pixel-clock"; 828 resets = <&ccu RST_BUS_TCON_LCD0>, 829 <&ccu RST_BUS_LVDS0>; 830 reset-names = "lcd", "lvds"; 831 #clock-cells = <0>; 832 833 ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 tcon_lcd0_in: port@0 { 838 reg = <0>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 842 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 843 reg = <0>; 844 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 845 }; 846 847 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 848 reg = <1>; 849 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 850 }; 851 }; 852 853 tcon_lcd0_out: port@1 { 854 reg = <1>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 858 tcon_lcd0_out_dsi: endpoint@1 { 859 reg = <1>; 860 remote-endpoint = <&dsi_in_tcon_lcd0>; 861 }; 862 }; 863 }; 864 }; 865 866 tcon_tv0: lcd-controller@5470000 { 867 compatible = "allwinner,sun20i-d1-tcon-tv"; 868 reg = <0x5470000 0x1000>; 869 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&ccu CLK_BUS_TCON_TV>, 871 <&tcon_top CLK_TCON_TOP_TV0>; 872 clock-names = "ahb", "tcon-ch1"; 873 resets = <&ccu RST_BUS_TCON_TV>; 874 reset-names = "lcd"; 875 876 ports { 877 #address-cells = <1>; 878 #size-cells = <0>; 879 880 tcon_tv0_in: port@0 { 881 reg = <0>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 886 reg = <0>; 887 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 888 }; 889 890 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 891 reg = <1>; 892 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 893 }; 894 }; 895 896 tcon_tv0_out: port@1 { 897 reg = <1>; 898 899 tcon_tv0_out_tcon_top_hdmi: endpoint { 900 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 901 }; 902 }; 903 }; 904 }; 905 906 ppu: power-controller@7001000 { 907 compatible = "allwinner,sun20i-d1-ppu"; 908 reg = <0x7001000 0x1000>; 909 clocks = <&r_ccu CLK_BUS_R_PPU>; 910 resets = <&r_ccu RST_BUS_R_PPU>; 911 #power-domain-cells = <1>; 912 }; 913 914 r_ccu: clock-controller@7010000 { 915 compatible = "allwinner,sun20i-d1-r-ccu"; 916 reg = <0x7010000 0x400>; 917 clocks = <&dcxo>, 918 <&rtc CLK_OSC32K>, 919 <&rtc CLK_IOSC>, 920 <&ccu CLK_PLL_PERIPH0_DIV3>; 921 clock-names = "hosc", "losc", "iosc", "pll-periph"; 922 #clock-cells = <1>; 923 #reset-cells = <1>; 924 }; 925 926 rtc: rtc@7090000 { 927 compatible = "allwinner,sun20i-d1-rtc", 928 "allwinner,sun50i-r329-rtc"; 929 reg = <0x7090000 0x400>; 930 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&r_ccu CLK_BUS_R_RTC>, 932 <&dcxo>, 933 <&r_ccu CLK_R_AHB>; 934 clock-names = "bus", "hosc", "ahb"; 935 #clock-cells = <1>; 936 }; 937 }; 938}; 939