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/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Ddma_ch_0_regs.h22 #define mmDMA_CH_0_CFG0 0x401000
24 #define mmDMA_CH_0_CFG1 0x401004
26 #define mmDMA_CH_0_ERRMSG_ADDR_LO 0x401008
28 #define mmDMA_CH_0_ERRMSG_ADDR_HI 0x40100C
30 #define mmDMA_CH_0_ERRMSG_WDATA 0x401010
32 #define mmDMA_CH_0_RD_COMP_ADDR_LO 0x401014
34 #define mmDMA_CH_0_RD_COMP_ADDR_HI 0x401018
36 #define mmDMA_CH_0_RD_COMP_WDATA 0x40101C
38 #define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020
40 #define mmDMA_CH_0_WR_COMP_ADDR_HI 0x401024
[all …]
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/cfg/
Dbz.c19 #define IWL_BZ_NVM_VERSION 0x0a1d
22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET 0x880000
25 #define IWL_BZ_DCCM2_LEN 0x8000
26 #define IWL_BZ_SMEM_OFFSET 0x400000
27 #define IWL_BZ_SMEM_LEN 0xD0000
82 .mac_addr_from_csr = 0x30, \
88 .min_umac_error_event_table = 0xD0000, \
89 .d3_debug_data_base_addr = 0x401000, \
[all …]
Dsc.c19 #define IWL_SC_NVM_VERSION 0x0a1d
22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_SC_DCCM2_OFFSET 0x880000
25 #define IWL_SC_DCCM2_LEN 0x8000
26 #define IWL_SC_SMEM_OFFSET 0x400000
27 #define IWL_SC_SMEM_LEN 0xD0000
91 .mac_addr_from_csr = 0x30, \
97 .min_umac_error_event_table = 0xD0000, \
98 .d3_debug_data_base_addr = 0x401000, \
[all …]
D9000.c19 #define IWL9000_NVM_VERSION 0x0a1d
22 #define IWL9000_DCCM_OFFSET 0x800000
23 #define IWL9000_DCCM_LEN 0x18000
24 #define IWL9000_DCCM2_OFFSET 0x880000
25 #define IWL9000_DCCM2_LEN 0x8000
26 #define IWL9000_SMEM_OFFSET 0x400000
27 #define IWL9000_SMEM_LEN 0x68000
92 .mac_addr_from_csr = 0x380, \
95 .min_umac_error_event_table = 0x800000, \
96 .d3_debug_data_base_addr = 0x401000, \
[all …]
Dax210.c19 #define IWL_AX210_NVM_VERSION 0x0a1d
22 #define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_AX210_DCCM2_OFFSET 0x880000
25 #define IWL_AX210_DCCM2_LEN 0x8000
26 #define IWL_AX210_SMEM_OFFSET 0x400000
27 #define IWL_AX210_SMEM_LEN 0xD0000
96 .mac_addr_from_csr = 0x380, \
103 .min_umac_error_event_table = 0x400000, \
104 .d3_debug_data_base_addr = 0x401000, \
[all …]
D22000.c19 #define IWL_22000_NVM_VERSION 0x0a1d
22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
24 #define IWL_22000_DCCM2_OFFSET 0x880000
25 #define IWL_22000_DCCM2_LEN 0x8000
26 #define IWL_22000_SMEM_OFFSET 0x400000
27 #define IWL_22000_SMEM_LEN 0xD0000
84 .mac_addr_from_csr = 0x380, \
91 .min_umac_error_event_table = 0x400000, \
92 .d3_debug_data_base_addr = 0x401000, \
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml34 pattern: "^switch@[0-9a-f]+$"
83 const: 0
86 "^port@[0-9a-f]+$":
111 minimum: 0
142 reg = <0 0x401000>,
143 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>;
148 resets = <&reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/microchip/
Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/aarch64/
Dvgic_init.c21 #define GICR_TYPER 0x8
55 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get()
61 GUEST_SYNC(0); in guest_code()
70 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu()
112 .size = 0x10000,
113 .alignment = 0x10000,
118 .size = NR_VCPUS * 0x20000,
119 .alignment = 0x10000,
124 .size = 0x1000,
125 .alignment = 0x1000,
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_2_0_offset.h26 // base address: 0x0
27 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
28 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
29 …BIF_CFG_DEV0_RC_COMMAND 0x0004
30 …BIF_CFG_DEV0_RC_STATUS 0x0006
31 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
32 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
33 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
34 …BIF_CFG_DEV0_RC_BASE_CLASS 0x000b
35 …BIF_CFG_DEV0_RC_CACHE_LINE 0x000c
[all …]
Dnbio_7_7_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_4 0x0078
34 // base address: 0x0
35 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
36 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
37 …BIF_CFG_DEV0_RC_COMMAND 0x0004
38 …BIF_CFG_DEV0_RC_STATUS 0x0006
39 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
40 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
41 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
[all …]