Lines Matching +full:0 +full:x401000

19 #define IWL_SC_NVM_VERSION		0x0a1d
22 #define IWL_SC_DCCM_OFFSET		0x800000 /* LMAC1 */
23 #define IWL_SC_DCCM_LEN			0x10000 /* LMAC1 */
24 #define IWL_SC_DCCM2_OFFSET		0x880000
25 #define IWL_SC_DCCM2_LEN		0x8000
26 #define IWL_SC_SMEM_OFFSET		0x400000
27 #define IWL_SC_SMEM_LEN			0xD0000
91 	.mac_addr_from_csr = 0x30,					\
97 	.min_umac_error_event_table = 0xD0000,				\
98 	.d3_debug_data_base_addr = 0x401000,				\
110 	.trans.umac_prph_offset = 0x300000,				\
114 	.gp2_reg_addr = 0xd02c68,					\
123 			.mask = 0xffffffff,				\
157 	.umac_prph_offset = 0x300000,