| /linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/ ! |
| D | cpu_ca53_cfg_masks.h | 23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
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| /linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/ ! |
| D | halbtc8822bwifionly.c | 9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
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| /linux-6.12.1/drivers/clk/rockchip/ ! |
| D | clk.h | 29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
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| /linux-6.12.1/drivers/media/pci/bt8xx/ ! |
| D | bttv-audio-hook.c | 30 for (loops = 17; loops >= 0 ; loops--) { in winview_volume()
70 gpio_inout(0x300, 0x300); in gvbctv3pci_audio()
74 con = 0x000; in gvbctv3pci_audio()
77 con = 0x300; in gvbctv3pci_audio()
80 con = 0x200; in gvbctv3pci_audio()
83 gpio_bits(0x300, con); in gvbctv3pci_audio()
97 con = 0x300; in gvbctv5pci_audio()
100 con = 0x100; in gvbctv5pci_audio()
103 con = 0x000; in gvbctv5pci_audio()
106 if (con != (val & 0x300)) { in gvbctv5pci_audio()
[all …]
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| /linux-6.12.1/drivers/media/dvb-frontends/ ! |
| D | dib0090.c | 25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
40 #define EN_LNA0 0x8000
41 #define EN_LNA1 0x4000
42 #define EN_LNA2 0x2000
43 #define EN_LNA3 0x1000
44 #define EN_MIX0 0x0800
45 #define EN_MIX1 0x0400
46 #define EN_MIX2 0x0200
47 #define EN_MIX3 0x0100
[all …]
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| /linux-6.12.1/arch/arm/mach-orion5x/ ! |
| D | bridge-regs.h | 9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
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| /linux-6.12.1/arch/sh/drivers/pci/ ! |
| D | fixups-snapgear.c | 26 case 11: irq = evt2irq(0x300); break; /* USB */ in pcibios_map_platform_irq()
27 case 12: irq = evt2irq(0x360); break; /* PCMCIA */ in pcibios_map_platform_irq()
28 case 13: irq = evt2irq(0x2a0); break; /* eth0 */ in pcibios_map_platform_irq()
29 case 14: irq = evt2irq(0x300); break; /* eth1 */ in pcibios_map_platform_irq()
30 case 15: irq = evt2irq(0x360); break; /* safenet (unused) */ in pcibios_map_platform_irq()
|
| /linux-6.12.1/arch/arm/boot/dts/microchip/ ! |
| D | sama5d3_can.dtsi | 36 reg = <0xf000c000 0x300>;
39 pinctrl-0 = <&pinctrl_can0_rx_tx>;
47 reg = <0xf8010000 0x300>;
50 pinctrl-0 = <&pinctrl_can1_rx_tx>;
|
| D | at91sam9x5_can.dtsi | 17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
|
| /linux-6.12.1/drivers/regulator/ ! |
| D | mt6357-regulator.c | 53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
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| /linux-6.12.1/include/dt-bindings/clock/ ! |
| D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ ! |
| D | gfx_7_2_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
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| D | gfx_8_0_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
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| D | gfx_8_1_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
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| /linux-6.12.1/arch/sh/boards/mach-se/7206/ ! |
| D | setup.c | 20 [0] = {
22 .start = PA_SMSC + 0x300,
23 .end = PA_SMSC + 0x300 + 0x020 - 1,
42 .coherent_dma_mask = 0xffffffff,
|
| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ ! |
| D | arasan,sdhci.yaml | 137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
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| /linux-6.12.1/arch/mips/kernel/ ! |
| D | cevt-ds1287.c | 17 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; in ds1287_timer_state()
26 rate = 0x9; in ds1287_set_base_clock()
29 rate = 0x8; in ds1287_set_base_clock()
32 rate = 0x6; in ds1287_set_base_clock()
40 return 0; in ds1287_set_base_clock()
60 return 0; in ds1287_shutdown()
74 return 0; in ds1287_set_periodic()
112 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); in ds1287_clockevent_init()
113 cd->max_delta_ticks = 0x7fffffff; in ds1287_clockevent_init()
114 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); in ds1287_clockevent_init()
[all …]
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| D | cevt-gt641xx.c | 27 return 0; in gt641xx_timer0_state()
51 return 0; in gt641xx_timer0_set_next_event()
65 return 0; in gt641xx_timer0_shutdown()
80 return 0; in gt641xx_timer0_set_oneshot()
94 return 0; in gt641xx_timer0_set_periodic()
128 return 0; in gt641xx_timer0_clockevent_init()
135 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); in gt641xx_timer0_clockevent_init()
136 cd->max_delta_ticks = 0x7fffffff; in gt641xx_timer0_clockevent_init()
137 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); in gt641xx_timer0_clockevent_init()
138 cd->min_delta_ticks = 0x300; in gt641xx_timer0_clockevent_init()
[all …]
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| /linux-6.12.1/drivers/net/phy/ ! |
| D | mediatek-ge.c | 6 #define MTK_EXT_PAGE_ACCESS 0x1f
7 #define MTK_PHY_PAGE_STANDARD 0x0000
8 #define MTK_PHY_PAGE_EXTENDED 0x0001
9 #define MTK_PHY_PAGE_EXTENDED_2 0x0002
10 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
11 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
12 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
27 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); in mtk_gephy_config_init()
31 __phy_write(phydev, 0x10, 0xafae); in mtk_gephy_config_init()
32 __phy_write(phydev, 0x12, 0x2f); in mtk_gephy_config_init()
[all …]
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| /linux-6.12.1/arch/sh/boards/mach-sdk7780/ ! |
| D | setup.c | 18 #define GPIO_PECR 0xFFEA0008
36 [0] = {
38 .start = PA_LAN + 0x300,
39 .end = PA_LAN + 0x300 + 0x10 ,
51 .id = 0,
54 .coherent_dma_mask = 0xffffffff,
80 (ver >> 12) & 0xf, (ver >> 8) & 0xf, in sdk7780_setup()
81 (ver >> 4) & 0xf, ver & 0xf, in sdk7780_setup()
85 __raw_writew(0x0000, GPIO_PECR); in sdk7780_setup()
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| /linux-6.12.1/arch/sh/boards/mach-se/7780/ ! |
| D | setup.c | 32 [0] = {
34 .start = PA_LAN + 0x300,
35 .end = PA_LAN + 0x300 + 0x10 ,
47 .id = 0,
50 .coherent_dma_mask = 0xffffffff,
68 #define GPIO_PHCR 0xFFEA000E
69 #define GPIO_PMSELR 0xFFEA0080
70 #define GPIO_PECR 0xFFEA0008
93 __raw_writew(0x0213, FPGA_REQSEL); in se7780_setup()
96 __raw_writew(0x0000, GPIO_PECR); in se7780_setup()
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/ralink/ ! |
| D | mt7628a.dtsi | 10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/ ! |
| D | akebono.dts | 14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/ ! |
| D | bif_4_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
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| /linux-6.12.1/drivers/media/pci/mgb4/ ! |
| D | mgb4_sysfs_in.c | 39 i2c_reg = MGB4_IS_GMSL(mgbdev) ? 0x1CE : 0x49; in oldi_lane_width_show()
40 i2c_mask = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x03; in oldi_lane_width_show()
41 i2c_single_val = MGB4_IS_GMSL(mgbdev) ? 0x00 : 0x02; in oldi_lane_width_show()
42 i2c_dual_val = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x00; in oldi_lane_width_show()
47 if (ret < 0) in oldi_lane_width_show()
58 return sprintf(buf, "%s\n", config & (1U << 9) ? "1" : "0"); in oldi_lane_width_show()
83 case 0: /* single */ in oldi_lane_width_store()
84 fpga_data = 0; in oldi_lane_width_store()
85 i2c_data = MGB4_IS_GMSL(mgbdev) ? 0x00 : 0x02; in oldi_lane_width_store()
89 i2c_data = MGB4_IS_GMSL(mgbdev) ? 0x0E : 0x00; in oldi_lane_width_store()
[all …]
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