Lines Matching +full:0 +full:x300
25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
40 #define EN_LNA0 0x8000
41 #define EN_LNA1 0x4000
42 #define EN_LNA2 0x2000
43 #define EN_LNA3 0x1000
44 #define EN_MIX0 0x0800
45 #define EN_MIX1 0x0400
46 #define EN_MIX2 0x0200
47 #define EN_MIX3 0x0100
48 #define EN_IQADC 0x0040
49 #define EN_PLL 0x0020
50 #define EN_TX 0x0010
51 #define EN_BB 0x0008
52 #define EN_LO 0x0004
53 #define EN_BIAS 0x0001
55 #define EN_IQANA 0x0002
56 #define EN_DIGCLK 0x0080 /* not in the 0x24 reg, only in 0x1b */
57 #define EN_CRYSTAL 0x0002
59 #define EN_UHF 0x22E9
60 #define EN_VHF 0x44E9
61 #define EN_LBD 0x11E9
62 #define EN_SBD 0x44E9
63 #define EN_CAB 0x88E9
66 #define DC_CAL 0x1
67 #define WBD_CAL 0x2
68 #define TEMP_CAL 0x4
69 #define CAPTRIM_CAL 0x8
71 #define KROSUS_PLL_LOCKED 0x800
72 #define KROSUS 0x2
75 #define SOC 0x02
76 #define SOC_7090_P1G_11R1 0x82
77 #define SOC_7090_P1G_21R1 0x8a
78 #define SOC_8090_P1G_11R1 0x86
79 #define SOC_8090_P1G_21R1 0x8e
82 #define P1A_B 0x0
83 #define P1C 0x1
84 #define P1D_E_F 0x3
85 #define P1G 0x7
86 #define P1G_21R2 0xf
88 #define MP001 0x1 /* Single 9090/8096 */
89 #define MP005 0x4 /* Single Sband */
90 #define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
91 #define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
204 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_read_reg()
206 return 0; in dib0090_read_reg()
209 state->i2c_write_buffer[0] = reg; in dib0090_read_reg()
211 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib0090_read_reg()
212 state->msg[0].addr = state->config->i2c_address; in dib0090_read_reg()
213 state->msg[0].flags = 0; in dib0090_read_reg()
214 state->msg[0].buf = state->i2c_write_buffer; in dib0090_read_reg()
215 state->msg[0].len = 1; in dib0090_read_reg()
223 ret = 0; in dib0090_read_reg()
225 ret = (state->i2c_read_buffer[0] << 8) in dib0090_read_reg()
236 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_write_reg()
241 state->i2c_write_buffer[0] = reg & 0xff; in dib0090_write_reg()
243 state->i2c_write_buffer[2] = val & 0xff; in dib0090_write_reg()
245 memset(state->msg, 0, sizeof(struct i2c_msg)); in dib0090_write_reg()
246 state->msg[0].addr = state->config->i2c_address; in dib0090_write_reg()
247 state->msg[0].flags = 0; in dib0090_write_reg()
248 state->msg[0].buf = state->i2c_write_buffer; in dib0090_write_reg()
249 state->msg[0].len = 3; in dib0090_write_reg()
255 ret = 0; in dib0090_write_reg()
265 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_read_reg()
267 return 0; in dib0090_fw_read_reg()
270 state->i2c_write_buffer[0] = reg; in dib0090_fw_read_reg()
272 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_read_reg()
279 ret = 0; in dib0090_fw_read_reg()
281 ret = (state->i2c_read_buffer[0] << 8) in dib0090_fw_read_reg()
292 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_write_reg()
297 state->i2c_write_buffer[0] = val >> 8; in dib0090_fw_write_reg()
298 state->i2c_write_buffer[1] = val & 0xff; in dib0090_fw_write_reg()
300 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_write_reg()
302 state->msg.flags = 0; in dib0090_fw_write_reg()
309 ret = 0; in dib0090_fw_write_reg()
315 … (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); m…
333 v = dib0090_read_reg(state, 0x1a); in dib0090_identify()
335 identity->p1g = 0; in dib0090_identify()
336 identity->in_soc = 0; in dib0090_identify()
338 dprintk("Tuner identification (Version = 0x%04x)\n", v); in dib0090_identify()
343 identity->version = v & 0xff; in dib0090_identify()
344 identity->product = (v >> 8) & 0xf; in dib0090_identify()
349 if ((identity->version & 0x3) == SOC) { in dib0090_identify()
372 switch ((identity->version >> 5) & 0x7) { in dib0090_identify()
389 switch (identity->version & 0x1f) { in dib0090_identify()
413 return 0; in dib0090_identify()
424 u16 v = dib0090_fw_read_reg(state, 0x1a); in dib0090_fw_identify()
425 identity->p1g = 0; in dib0090_fw_identify()
426 identity->in_soc = 0; in dib0090_fw_identify()
428 dprintk("FE: Tuner identification (Version = 0x%04x)\n", v); in dib0090_fw_identify()
433 identity->version = v & 0xff; in dib0090_fw_identify()
434 identity->product = (v >> 8) & 0xf; in dib0090_fw_identify()
439 if ((identity->version & 0x3) == SOC) { in dib0090_fw_identify()
462 switch ((identity->version >> 5) & 0x7) { in dib0090_fw_identify()
479 switch (identity->version & 0x1f) { in dib0090_fw_identify()
503 return 0; in dib0090_fw_identify()
515 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_reset_digital()
519 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remai… in dib0090_reset_digital()
521 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <… in dib0090_reset_digital()
522 if (cfg->clkoutdrive != 0) in dib0090_reset_digital()
523 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
524 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0)); in dib0090_reset_digital()
526 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
527 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0)); in dib0090_reset_digital()
530 PllCfg = dib0090_read_reg(state, 0x21); in dib0090_reset_digital()
533 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr… in dib0090_reset_digital()
538 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
542 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
545 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io… in dib0090_reset_digital()
546 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
550 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
555 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); in dib0090_reset_digital()
560 if (i == 0) { in dib0090_reset_digital()
567 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
572 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
586 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_fw_reset_digital()
587 …dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL re… in dib0090_fw_reset_digital()
589 dib0090_fw_write_reg(state, 0x20, in dib0090_fw_reset_digital()
590 …((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) … in dib0090_fw_reset_digital()
592 …v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | … in dib0090_fw_reset_digital()
593 if (cfg->clkoutdrive != 0) in dib0090_fw_reset_digital()
599 dib0090_fw_write_reg(state, 0x23, v); in dib0090_fw_reset_digital()
602 PllCfg = dib0090_fw_read_reg(state, 0x21); in dib0090_fw_reset_digital()
605 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr… in dib0090_fw_reset_digital()
609 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
613 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
616 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io… in dib0090_fw_reset_digital()
617 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
621 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
626 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800); in dib0090_fw_reset_digital()
631 if (i == 0) { in dib0090_fw_reset_digital()
638 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
643 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
653 state->config->sleep(fe, 0); in dib0090_wakeup()
656 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_wakeup()
657 return 0; in dib0090_wakeup()
665 return 0; in dib0090_sleep()
672 dib0090_write_reg(state, 0x04, 0); in dib0090_dcc_freq()
674 dib0090_write_reg(state, 0x04, 1); in dib0090_dcc_freq()
683 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
684 (0 << 9) | 208, /* BB_RAMP4 */
686 (0 << 9) | 440, /* BB_RAMP6 */
694 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
696 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
698 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
699 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
700 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
708 (0 << 10) | 746, /* RF_RAMP6, LNA 1 */
709 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
710 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
712 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
713 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
714 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
721 (0 << 10) | 0, /* RF_RAMP5, LNA 1 = 8dB */ /* 7.47 dB */
722 (0 << 10) | 0, /* RF_RAMP6, LNA 1 */
723 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
724 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
726 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
727 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
728 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
736 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
738 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
740 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
741 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
742 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
749 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
750 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
752 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
754 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
756 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
763 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
764 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
766 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
768 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
770 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
778 (2 << 9) | 0, /* BB_RAMP3 = 21dB */
779 (0 << 9) | 168, /* BB_RAMP4 */
781 (0 << 9) | 400, /* BB_RAMP6 */
784 #if 0
790 (2 << 9) | 0, /* BB_RAMP3 = 26dB */
791 (0 << 9) | 208, /* BB_RAMP4 */
793 (0 << 9) | 440, /* BB_RAMP6 */
801 (8 << 10) | 743, /* RF_RAMP3, LNA 1 = 0dB */
802 (0 << 10) | 1023, /* RF_RAMP4, LNA 1 */
803 (15 << 10) | 469, /* RF_RAMP5, LNA 2 = 0dB */
804 (0 << 10) | 742, /* RF_RAMP6, LNA 2 */
805 (9 << 10) | 234, /* RF_RAMP7, LNA 3 = 0dB */
806 (0 << 10) | 468, /* RF_RAMP8, LNA 3 */
807 (9 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
808 (0 << 10) | 233, /* GAIN_4_2, LNA 4 */
815 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
816 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
818 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
820 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
822 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
829 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
830 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
832 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
834 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
836 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
839 #if 0
845 (4 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.1dB */
846 (0 << 10) | 508, /* RF_RAMP4, LNA 1 */
848 (0 << 10) | 961, /* RF_RAMP6, LNA 2 */
849 (0 << 10) | 0, /* RF_RAMP7, LNA 3 = 0dB */
850 (0 << 10) | 0, /* RF_RAMP8, LNA 3 */
851 (0 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
852 (0 << 10) | 0, /* GAIN_4_2, LNA 4 */
864 u16 ret = 0; in slopes_to_scale()
865 for (i = 0; i < num; i++) { in slopes_to_scale()
884 wbd &= 0x3ff; in dib0090_wbd_to_db()
886 wbd = 0; in dib0090_wbd_to_db()
913 0x08, 0x0a, 0x0f, 0x01
919 u16 i, v, gain_reg[4] = { 0 }, gain; in dib0090_gain_apply()
932 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */ in dib0090_gain_apply()
933 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_apply()
937 if (state->rf_gain_limit < 0) /*underflow */ in dib0090_gain_apply()
938 state->rf_gain_limit = 0; in dib0090_gain_apply()
941 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA; in dib0090_gain_apply()
946 /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */ in dib0090_gain_apply()
947 if (state->current_gain < 0) in dib0090_gain_apply()
948 state->current_gain = 0; in dib0090_gain_apply()
957 if (bb > state->bb_ramp[0]) in dib0090_gain_apply()
958 bb = state->bb_ramp[0]; in dib0090_gain_apply()
961 bb = 0; in dib0090_gain_apply()
964 state->gain[0] = rf; in dib0090_gain_apply()
971 for (i = 0; i < 7; i++) { /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */ in dib0090_gain_apply()
972 …if (g[0] == 0 || ref < (g[1] - g[0])) /* if total gain of the current amp is null or this amp is n… in dib0090_gain_apply()
973 v = 0; /* force the gain to write for the current amp to be null */ in dib0090_gain_apply()
977 v = ((ref - (g[1] - g[0])) * g[2]) / g[0]; in dib0090_gain_apply()
979 if (i == 0) /* LNA 1 reg mapping */ in dib0090_gain_apply()
980 gain_reg[0] = v; in dib0090_gain_apply()
982 gain_reg[0] |= v << 7; in dib0090_gain_apply()
1006 …tk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_r… in dib0090_gain_apply()
1007 gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]); in dib0090_gain_apply()
1011 for (i = 0; i < 4; i++) { in dib0090_gain_apply()
1022 state->bb_1_def &= 0xdfff; in dib0090_set_boost()
1035 dib0090_write_reg(state, 0x2a, 0xffff); in dib0090_set_rframp_pwm()
1037 dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); in dib0090_set_rframp_pwm()
1039 dib0090_write_regs(state, 0x2c, cfg + 3, 6); in dib0090_set_rframp_pwm()
1040 dib0090_write_regs(state, 0x3e, cfg + 9, 2); in dib0090_set_rframp_pwm()
1046 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp()
1053 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp_pwm()
1055 dib0090_write_reg(state, 0x33, 0xffff); in dib0090_set_bbramp_pwm()
1056 dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33)); in dib0090_set_bbramp_pwm()
1057 dib0090_write_regs(state, 0x35, cfg + 3, 4); in dib0090_set_bbramp_pwm()
1110 state->rf_ramp[0], in dib0090_pwm_gain_reset()
1112 state->identity.version & 0x1f); in dib0090_pwm_gain_reset()
1114 if (rf_ramp && ((state->rf_ramp && state->rf_ramp[0] == 0) || in dib0090_pwm_gain_reset()
1116 (state->identity.version & 0x1f) <= P1D_E_F))) { in dib0090_pwm_gain_reset()
1118 en_pwm_rf_mux = 0; in dib0090_pwm_gain_reset()
1122 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); in dib0090_pwm_gain_reset()
1124 …/* Set fast servo cutoff to start AGC; 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fas… in dib0090_pwm_gain_reset()
1126 dib0090_write_reg(state, 0x04, 3); in dib0090_pwm_gain_reset()
1128 dib0090_write_reg(state, 0x04, 1); in dib0090_pwm_gain_reset()
1129 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ in dib0090_pwm_gain_reset()
1138 dib0090_write_reg(state, 0x04, DC_servo_cutoff); in dib0090_set_dc_servo()
1144 u16 adc_val = dib0090_read_reg(state, 0x1d); in dib0090_get_slow_adc_val()
1156 u16 wbd_val = 0; in dib0090_gain_control()
1158 s16 wbd_error = 0, adc_error = 0; in dib0090_gain_control()
1161 state->agc_freeze = 0; in dib0090_gain_control()
1162 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1190 dib0090_write_reg(state, 0x32, 0); in dib0090_gain_control()
1191 dib0090_write_reg(state, 0x39, 0); in dib0090_gain_control()
1195 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_control()
1196 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA; in dib0090_gain_control()
1200 s16 wbd = 0, i, cnt; in dib0090_gain_control()
1210 for (i = 0; i < cnt; i++) { in dib0090_gain_control()
1218 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) { in dib0090_gain_control()
1221 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; in dib0090_gain_control()
1224 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */ in dib0090_gain_control()
1228 state->agc_step = 0; in dib0090_gain_control()
1234 adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */ in dib0090_gain_control()
1247 …ty_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > in dib0090_gain_control()
1248 0) in dib0090_gain_control()
1250 ((state->fe->dtv_property_cache.layer[0].modulation == in dib0090_gain_control()
1253 layer[0].modulation == QAM_16))) in dib0090_gain_control()
1256 0) in dib0090_gain_control()
1264 0) in dib0090_gain_control()
1280 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : nar… in dib0090_gain_control()
1281 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1285 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); in dib0090_gain_control()
1286 …dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_gain_control()
1294 apply_gain_immediatly = 0; in dib0090_gain_control()
1317 *rf = state->gain[0]; in dib0090_get_current_gain()
1323 *rflt = (state->rf_lt_def >> 10) & 0x7; in dib0090_get_current_gain()
1341 if (current_temp < 0) in dib0090_get_wbd_target()
1342 current_temp = 0; in dib0090_get_wbd_target()
1347 if (wbd->wbd_gain != 0) in dib0090_get_wbd_target()
1352 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_get_wbd_target()
1378 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) in dib0090_set_switch()
1381 return 0; in dib0090_set_switch()
1389 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) in dib0090_set_vga()
1391 return 0; in dib0090_set_vga()
1412 return 0; in dib0090_update_rframp_7090()
1418 25, 0x01,
1419 0x0000,
1420 0x99a0,
1421 0x6008,
1422 0x0000,
1423 0x8bcb,
1424 0x0000,
1425 0x0405,
1426 0x0000,
1427 0x0000,
1428 0x0000,
1429 0xb802,
1430 0x0300,
1431 0x2d12,
1432 0xbac0,
1433 0x7c00,
1434 0xdbb9,
1435 0x0954,
1436 0x0743,
1437 0x8000,
1438 0x0001,
1439 0x0040,
1440 0x0100,
1441 0x0000,
1442 0xe910,
1443 0x149e,
1445 1, 0x1c,
1446 0xff2d,
1448 1, 0x39,
1449 0x0000,
1451 2, 0x1e,
1452 0x07FF,
1453 0x0007,
1455 1, 0x24,
1458 2, 0x3c,
1459 0x3ff,
1460 0x111,
1461 0
1465 1, 0x05,
1466 0xabcd,
1468 1, 0x11,
1469 0x00b4,
1471 1, 0x1c,
1472 0xfffd,
1474 1, 0x40,
1475 0x108,
1476 0
1498 #define POLY_MIN (u8) 0
1507 e2 = dib0090_read_reg(state, 0x26); in dib0090_set_EFUSE()
1508 e4 = dib0090_read_reg(state, 0x28); in dib0090_set_EFUSE()
1511 (state->identity.version == P1G) || (e2 == 0xffff)) { in dib0090_set_EFUSE()
1513 dib0090_write_reg(state, 0x22, 0x10); in dib0090_set_EFUSE()
1514 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; in dib0090_set_EFUSE()
1525 if (e2 != 0xffff) { in dib0090_set_EFUSE()
1526 c = e2 & 0x3f; in dib0090_set_EFUSE()
1527 n = (e2 >> 12) & 0xf; in dib0090_set_EFUSE()
1528 h = (e2 >> 6) & 0x3f; in dib0090_set_EFUSE()
1539 dib0090_write_reg(state, 0x13, (h << 10)); in dib0090_set_EFUSE()
1541 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ in dib0090_set_EFUSE()
1550 if (dib0090_identify(fe) < 0) in dib0090_reset()
1554 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */ in dib0090_reset()
1555 return 0; in dib0090_reset()
1559 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) in dib0090_reset()
1560 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1562 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1568 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ in dib0090_reset()
1574 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) in dib0090_reset()
1578 if (state->config->force_crystal_mode != 0) in dib0090_reset()
1579 dib0090_write_reg(state, 0x14, in dib0090_reset()
1582 dib0090_write_reg(state, 0x14, 1); in dib0090_reset()
1584 dib0090_write_reg(state, 0x14, 2); in dib0090_reset()
1585 dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); in dib0090_reset()
1589 return 0; in dib0090_reset()
1601 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_get_offset()
1606 state->adc_diff = dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1609 dib0090_write_reg(state, 0x1f, 0x4); in dib0090_get_offset()
1614 state->adc_diff -= dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1616 ret = 0; in dib0090_get_offset()
1635 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1636 {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
1637 {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
1639 {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
1640 {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
1641 {0},
1645 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1647 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
1648 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
1650 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
1651 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
1652 {0},
1659 if (state->dc->addr == 0x07) in dib0090_set_trim()
1664 *val &= ~(0x1f << state->dc->offset); in dib0090_set_trim()
1672 int ret = 0; in dib0090_dc_offset_calibration()
1680 state->bb6 = 0; in dib0090_dc_offset_calibration()
1681 state->bb7 = 0x040d; in dib0090_dc_offset_calibration()
1684 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ in dib0090_dc_offset_calibration()
1685 dib0090_write_reg(state, 0x24, reg); in dib0090_dc_offset_calibration()
1687 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_dc_offset_calibration()
1688 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); in dib0090_dc_offset_calibration()
1689 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_dc_offset_calibration()
1700 dib0090_write_reg(state, 0x01, state->dc->bb1); in dib0090_dc_offset_calibration()
1701 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); in dib0090_dc_offset_calibration()
1703 state->step = 0; in dib0090_dc_offset_calibration()
1722 if (state->step == 0 && state->adc_diff < 0) { in dib0090_dc_offset_calibration()
1730 if (state->step == 0) { in dib0090_dc_offset_calibration()
1731 if (state->dc->pga && state->adc_diff < 0) in dib0090_dc_offset_calibration()
1732 state->step = 0x10; in dib0090_dc_offset_calibration()
1733 if (state->dc->pga == 0 && state->adc_diff > 0) in dib0090_dc_offset_calibration()
1734 state->step = 0x10; in dib0090_dc_offset_calibration()
1738 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) { in dib0090_dc_offset_calibration()
1739 …/* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuan… in dib0090_dc_offset_calibration()
1755 if (state->dc->addr == 0) /* done */ in dib0090_dc_offset_calibration()
1764 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); in dib0090_dc_offset_calibration()
1765 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_dc_offset_calibration()
1785 if (wbd->wbd_gain != 0) in dib0090_wbd_calibration()
1798 return 0; in dib0090_wbd_calibration()
1801 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); in dib0090_wbd_calibration()
1803 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); in dib0090_wbd_calibration()
1818 return 0; in dib0090_wbd_calibration()
1832 tmp = (0 << 14); in dib0090_set_bandwidth()
1834 state->bb_1_def &= 0x3fff; in dib0090_set_bandwidth()
1837 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ in dib0090_set_bandwidth()
1839 …dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte… in dib0090_set_bandwidth()
1840 …dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_set_bandwidth()
1842 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n… in dib0090_set_bandwidth()
1844 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ in dib0090_set_bandwidth()
1845 …dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias… in dib0090_set_bandwidth()
1851 {56000, 0, 9, 48, 6},
1853 {87000, 0, 8, 32, 4},
1855 {115000, 0, 7, 24, 6},
1857 {170000, 0, 6, 16, 4},
1861 {230000, 0, 5, 12, 6},
1863 {340000, 0, 4, 8, 4},
1865 {450000, 0, 3, 6, 6},
1869 {700000, 0, 2, 4, 4},
1873 {1800000, 1, 0, 2, 4},
1876 {2900000, 0, 14, 1, 4},
1883 {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1884 {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1885 {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1888 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1889 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1890 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1891 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1892 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1893 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1896 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1897 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1898 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1901 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1902 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1909 {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1912 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1913 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1914 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1917 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1918 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1919 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1920 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1921 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1922 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1925 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1926 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1927 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1930 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1931 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1937 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
1940 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1941 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1942 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1945 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1946 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1947 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1948 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1949 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1950 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1951 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1954 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1955 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1956 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1959 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1960 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1966 {57000, 0, 11, 48, 6},
1968 {86000, 0, 10, 32, 4},
1970 {115000, 0, 9, 24, 6},
1972 {170000, 0, 8, 16, 4},
1976 {230000, 0, 7, 12, 6},
1978 {340000, 0, 6, 8, 4},
1980 {455000, 0, 5, 6, 6},
1984 {680000, 0, 4, 4, 4},
1991 {2900000, 0, 1, 1, 6},
1997 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1998 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1999 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2002 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2003 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2004 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2005 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2006 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2007 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2010 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2011 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2012 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2015 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
2016 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
2022 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2023 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2024 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2025 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2031 { 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2032 { 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2033 { 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2034 { 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
2035 { 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2036 { 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
2047 { 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2048 { 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2049 { 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2067 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) in dib0090_update_tuning_table_7090()
2068 | (tune->lna_bias & 0x7fff)); in dib0090_update_tuning_table_7090()
2069 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) in dib0090_update_tuning_table_7090()
2070 | ((tune->lna_tune << 6) & 0x07c0)); in dib0090_update_tuning_table_7090()
2071 return 0; in dib0090_update_tuning_table_7090()
2077 int ret = 0; in dib0090_captrim_search()
2078 u16 lo4 = 0xe900; in dib0090_captrim_search()
2083 u8 force_soft_search = 0; in dib0090_captrim_search()
2091 dib0090_write_reg(state, 0x10, 0x2B1); in dib0090_captrim_search()
2092 dib0090_write_reg(state, 0x1e, 0x0032); in dib0090_captrim_search()
2104 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; in dib0090_captrim_search()
2114 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); in dib0090_captrim_search()
2115 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2119 dib0090_write_reg(state, 0x18, lo4 | state->captrim); in dib0090_captrim_search()
2128 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); in dib0090_captrim_search()
2129 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2131 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; in dib0090_captrim_search()
2132 dprintk("***Final Captrim= 0x%x\n", state->fcaptrim); in dib0090_captrim_search()
2140 …if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug… in dib0090_captrim_search()
2169 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); in dib0090_captrim_search()
2188 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_get_temperature()
2189 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); in dib0090_get_temperature()
2191 state->bias = dib0090_read_reg(state, 0x13); in dib0090_get_temperature()
2192 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); in dib0090_get_temperature()
2200 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); in dib0090_get_temperature()
2214 dib0090_write_reg(state, 0x13, state->bias); in dib0090_get_temperature()
2215 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ in dib0090_get_temperature()
2219 if (state->config->analog_output == 0) in dib0090_get_temperature()
2220 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_get_temperature()
2225 ret = 0; in dib0090_get_temperature()
2231 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
2240 u32 FBDiv, Rest, FREF, VCOF_kHz = 0; in dib0090_tune()
2253 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_tune()
2256 if (state->config->analog_output == 0) in dib0090_tune()
2257 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_tune()
2263 if (state->current_rf == 0) in dib0090_tune()
2272 …access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, oth… in dib0090_tune()
2274 tmp = dib0090_read_reg(state, 0x39); in dib0090_tune()
2275 if ((tmp >> 10) & 0x1) in dib0090_tune()
2276 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); in dib0090_tune()
2287 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) { in dib0090_tune()
2289 u8 found_offset = 0; in dib0090_tune()
2293 while (LUT_offset->RF_freq != 0xffff) { in dib0090_tune()
2305 if (found_offset == 0) in dib0090_tune()
2309 state->tuner_is_tuned = 0; in dib0090_tune()
2310 state->current_rf = 0; in dib0090_tune()
2311 state->current_standard = 0; in dib0090_tune()
2317 tmp = (state->identity.version >> 5) & 0x7; in dib0090_tune()
2339 if (tmp == 0x4 || tmp == 0x7) { in dib0090_tune()
2363 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); in dib0090_tune()
2368 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2375 Rest = 0; in dib0090_tune()
2379 Rest = 0; in dib0090_tune()
2387 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; in dib0090_tune()
2388 * lo6 = 0x0e34 */ in dib0090_tune()
2390 if (Rest == 0) { in dib0090_tune()
2392 lo5 = 0x049f; in dib0090_tune()
2394 lo5 = 0x041f; in dib0090_tune()
2397 lo5 = 0x049e; in dib0090_tune()
2399 lo5 = 0x041d; in dib0090_tune()
2401 lo5 = 0x041c; in dib0090_tune()
2407 lo5 = 0x46f; in dib0090_tune()
2409 lo5 = 0x42f; in dib0090_tune()
2411 lo5 = 0x42c; in dib0090_tune()
2418 lo6 = 0xff98; in dib0090_tune()
2419 else if (state->identity.p1g || (Rest == 0)) in dib0090_tune()
2420 lo6 = 0xfff8; in dib0090_tune()
2422 lo6 = 0xff28; in dib0090_tune()
2428 if (Rest > 0) { in dib0090_tune()
2432 dib0090_write_reg(state, 0x15, (u16) FBDiv); in dib0090_tune()
2433 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2434 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); in dib0090_tune()
2436 dib0090_write_reg(state, 0x16, (Den << 8) | 1); in dib0090_tune()
2437 dib0090_write_reg(state, 0x17, (u16) Rest); in dib0090_tune()
2438 dib0090_write_reg(state, 0x19, lo5); in dib0090_tune()
2439 dib0090_write_reg(state, 0x1c, lo6); in dib0090_tune()
2443 lo6 = (lo6 & 0xff9f) | 0x2; in dib0090_tune()
2445 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); in dib0090_tune()
2462 dib0090_write_reg(state, 0x1e, 0x07ff); in dib0090_tune()
2468 …k("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17… in dib0090_tune()
2469 …m: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x1… in dib0090_tune()
2470 (u32) dib0090_read_reg(state, 0x1c) & 0x3); in dib0090_tune()
2472 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ in dib0090_tune()
2476 if (wbd->wbd_gain != 0) in dib0090_tune()
2480 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_tune()
2484 dib0090_write_reg(state, 0x09, tune->lna_bias); in dib0090_tune()
2485 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); in dib0090_tune()
2487 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); in dib0090_tune()
2489 dib0090_write_reg(state, 0x0c, tune->v2i); in dib0090_tune()
2490 dib0090_write_reg(state, 0x0d, tune->mix); in dib0090_tune()
2491 dib0090_write_reg(state, 0x0e, tune->load); in dib0090_tune()
2496 state->rf_lt_def = 0x7c00; in dib0090_tune()
2529 return 0; in dib0090_set_tune_state()
2539 return 0; in dib0090_get_frequency()
2566 return 0; in dib0090_set_params()
2600 {470, 0, 250, 0, 100, 4},
2602 {1700, 0, 800, 0, 850, 4},
2603 {2900, 0, 250, 0, 100, 6},
2604 {0xFFFF, 0, 0, 0, 0, 0},
2624 if (dib0090_reset(fe) != 0) in dib0090_register()
2651 if (dib0090_fw_reset_digital(fe, st->config) != 0) in dib0090_fw_register()