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/linux-6.12.1/include/linux/mtd/
Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/sprd/
Dsprd,sc9863a-glbregs.yaml33 "@[0-9a-f]+$":
43 reg = <0x20e00000 0x4000>;
44 ranges = <0 0x20e00000 0x4000>;
48 apahb_gate: apahb-gate@0 {
50 reg = <0x0 0x1020>;
/linux-6.12.1/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux-6.12.1/drivers/mmc/host/
Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgpucc-msm8998.c35 .halt_reg = 0x1020,
37 .enable_reg = 0x1020,
38 .enable_mask = BIT(0),
52 { 249600000, 2000000000, 0 },
57 { 0x0, 1 },
58 { 0x1, 2 },
59 { 0x3, 4 },
60 { 0x7, 8 },
65 .offset = 0x0,
78 .offset = 0x0,
[all …]
Dgpucc-sdm660.c38 .halt_reg = 0x1020,
40 .enable_reg = 0x1020,
41 .enable_mask = BIT(0),
55 { 1000000000, 2000000000, 0 },
61 .offset = 0x0,
76 .offset = 0x40,
91 { P_GPU_XO, 0 },
107 .cmd_rcgr = 0x1070,
108 .mnd_width = 0,
127 .halt_reg = 0x1098,
[all …]
Ddispcc-sm6375.c39 { 249600000, 2000000000, 0 },
44 .l = 0x20,
45 .alpha = 0x800,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329a299c,
49 .user_ctl_val = 0x00000001,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
[all …]
Ddispcc-sm6350.c35 { 249600000, 2000000000, 0 },
39 .l = 0x3a,
40 .alpha = 0x5555,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002067,
43 .test_ctl_val = 0x40000000,
44 .test_ctl_hi_val = 0x00000002,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00004805,
50 .offset = 0x0,
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Ddcore0_tpc0_eml_spmu_regs.h23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsprd,sc9863a-clk.yaml81 reg = <0x21500000 0x1000>;
90 reg = <0x20e00000 0x4000>;
93 ranges = <0 0x20e00000 0x4000>;
95 apahb_gate: apahb-gate@0 {
97 reg = <0x0 0x1020>;
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux-6.12.1/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/linux-6.12.1/arch/sh/include/mach-common/mach/
Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/linux-6.12.1/include/uapi/linux/
Dmedia-bus-format.h16 * These bus formats uniquely identify data formats on the data bus. Format 0
35 #define MEDIA_BUS_FMT_FIXED 0x0001
37 /* RGB - next is 0x1026 */
38 #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
40 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
42 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
43 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017
44 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
[all …]
/linux-6.12.1/drivers/gpu/drm/hisilicon/kirin/
Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/linux-6.12.1/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux-6.12.1/drivers/gpu/drm/lima/
Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_mipi_dsi_regs.h11 #define LINKSR 0x010
13 #define LINKSR_HSBUSY (1 << 0)
18 #define TXVMSETR 0x180
19 #define TXVMSETR_SYNSEQ_PULSES (0 << 16)
24 #define TXVMSETR_VSEN_DIS (0 << 4)
26 #define TXVMSETR_HFPBPEN_DIS (0 << 2)
28 #define TXVMSETR_HBPBPEN_DIS (0 << 1)
29 #define TXVMSETR_HSABPEN_EN (1 << 0)
30 #define TXVMSETR_HSABPEN_DIS (0 << 0)
32 #define TXVMCR 0x190
[all …]
/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos-pcie.c18 #define PCIE_PHY_OFFSET(x) ((x) * 0x4)
21 #define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
22 #define PCIE_MAC_RESET_MASK 0xFF
24 #define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
25 #define PCIE_REFCLK_GATING_EN BIT(0)
26 #define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
27 #define PCIE_PHY_RESET BIT(0)
28 #define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
29 #define PCIE_GLOBAL_RESET BIT(0)
31 #define PCIE_REFCLK_MASK 0x16
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
27 apahb_gate: apahb-gate@0 {
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
42 pmu_gate: pmu-gate@0 {
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-loongson64/
Dloongson_regs.h25 "parse_r __res,%0\n\t" in read_cpucfg()
29 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" in read_cpucfg()
38 #define LOONGSON_CFG0 0x0
39 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
41 #define LOONGSON_CFG1 0x1
42 #define LOONGSON_CFG1_FP BIT(0)
74 #define LOONGSON_CFG2 0x2
75 #define LOONGSON_CFG2_LEXT1 BIT(0)
104 #define LOONGSON_CFG3 0x3
105 #define LOONGSON_CFG3_LCAMP BIT(0)
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/
Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]

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