clk/qcom/dispcc-sm6350.c

35 	{ 249600000, 2000000000, 0 },
39 	.l = 0x3a,
40 	.alpha = 0x5555,
41 	.config_ctl_val = 0x20485699,
42 	.config_ctl_hi_val = 0x00002067,
43 	.test_ctl_val = 0x40000000,
44 	.test_ctl_hi_val = 0x00000002,
45 	.user_ctl_val = 0x00000000,
46 	.user_ctl_hi_val = 0x00004805,
50 	.offset = 0x0,
67 	{ P_BI_TCXO, 0 },
79 	{ P_BI_TCXO, 0 },
89 	{ P_BI_TCXO, 0 },
103 	{ P_BI_TCXO, 0 },
113 	{ P_BI_TCXO, 0 },
123 	{ P_BI_TCXO, 0 },
131 	F(19200000, P_BI_TCXO, 1, 0, 0),
132 	F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
133 	F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
138 	.cmd_rcgr = 0x115c,
139 	.mnd_width = 0,
153 	.cmd_rcgr = 0x10c4,
154 	.mnd_width = 0,
167 	.reg = 0x10dc,
168 	.shift = 0,
182 	F(19200000, P_BI_TCXO, 1, 0, 0),
187 	.cmd_rcgr = 0x1144,
188 	.mnd_width = 0,
202 	F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
203 	F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
204 	F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
205 	F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
210 	.cmd_rcgr = 0x1114,
211 	.mnd_width = 0,
225 	.cmd_rcgr = 0x10f8,
226 	.mnd_width = 0,
239 	.cmd_rcgr = 0x112c,
253 	.cmd_rcgr = 0x10e0,
254 	.mnd_width = 0,
267 	F(19200000, P_BI_TCXO, 1, 0, 0),
268 	F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
269 	F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
270 	F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
271 	F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
272 	F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
277 	.cmd_rcgr = 0x107c,
278 	.mnd_width = 0,
292 	.cmd_rcgr = 0x1064,
306 	.cmd_rcgr = 0x1094,
307 	.mnd_width = 0,
321 	.cmd_rcgr = 0x10ac,
322 	.mnd_width = 0,
335 	.reg = 0x1110,
336 	.shift = 0,
350 	.halt_reg = 0x104c,
353 		.enable_reg = 0x104c,
354 		.enable_mask = BIT(0),
368 	.halt_reg = 0x102c,
371 		.enable_reg = 0x102c,
372 		.enable_mask = BIT(0),
386 	.halt_reg = 0x1030,
389 		.enable_reg = 0x1030,
390 		.enable_mask = BIT(0),
404 	.halt_reg = 0x1048,
407 		.enable_reg = 0x1048,
408 		.enable_mask = BIT(0),
422 	.halt_reg = 0x1040,
425 		.enable_reg = 0x1040,
426 		.enable_mask = BIT(0),
440 	.halt_reg = 0x1038,
443 		.enable_reg = 0x1038,
444 		.enable_mask = BIT(0),
458 	.halt_reg = 0x103c,
461 		.enable_reg = 0x103c,
462 		.enable_mask = BIT(0),
476 	.halt_reg = 0x1044,
479 		.enable_reg = 0x1044,
480 		.enable_mask = BIT(0),
494 	.halt_reg = 0x1034,
497 		.enable_reg = 0x1034,
498 		.enable_mask = BIT(0),
512 	.halt_reg = 0x1010,
515 		.enable_reg = 0x1010,
516 		.enable_mask = BIT(0),
530 	.halt_reg = 0x1020,
533 		.enable_reg = 0x1020,
534 		.enable_mask = BIT(0),
548 	.halt_reg = 0x2004,
551 		.enable_reg = 0x2004,
552 		.enable_mask = BIT(0),
566 	.halt_reg = 0x100c,
569 		.enable_reg = 0x100c,
570 		.enable_mask = BIT(0),
584 	.halt_reg = 0x1018,
587 		.enable_reg = 0x1018,
588 		.enable_mask = BIT(0),
602 	.halt_reg = 0x200c,
605 		.enable_reg = 0x200c,
606 		.enable_mask = BIT(0),
620 	.halt_reg = 0x2008,
623 		.enable_reg = 0x2008,
624 		.enable_mask = BIT(0),
638 	.halt_reg = 0x1028,
641 		.enable_reg = 0x1028,
642 		.enable_mask = BIT(0),
656 	.halt_reg = 0x5004,
659 		.enable_reg = 0x5004,
660 		.enable_mask = BIT(0),
669 	.halt_reg = 0x5008,
672 		.enable_reg = 0x5008,
673 		.enable_mask = BIT(0),
683 	.gdscr = 0x1004,
736 	.max_register = 0x10000,