Lines Matching +full:0 +full:x1020
22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
27 apahb_gate: apahb-gate@0 {
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
42 pmu_gate: pmu-gate@0 {
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
59 aonapb_gate: aonapb-gate@0 {
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
72 ranges = <0 0 0x40353000 0x3000>;
74 pll: pll@0 {
76 reg = <0 0x100>;
86 reg = <0 0x40359000 0 0x3000>;
89 ranges = <0 0 0x40359000 0x3000>;
91 mpll: mpll@0 {
93 reg = <0 0x100>;
101 reg = <0 0x4035c000 0 0x3000>;
104 ranges = <0 0 0x4035c000 0x3000>;
106 rpll: rpll@0 {
108 reg = <0 0x100>;
118 reg = <0 0x40363000 0 0x3000>;
121 ranges = <0 0 0x40363000 0x3000>;
123 dpll: dpll@0 {
125 reg = <0 0x100>;
133 reg = <0 0x60800000 0 0x1000>;
136 ranges = <0 0 0x60800000 0x3000>;
138 mm_gate: mm-gate@0 {
140 reg = <0 0x1100>;
148 reg = <0 0x71300000 0 0x4000>;
151 ranges = <0 0 0x71300000 0x4000>;
153 apapb_gate: apapb-gate@0 {
155 reg = <0 0x1000>;
166 ranges = <0 0x0 0x70000000 0x10000000>;
168 uart0: serial@0 {
171 reg = <0x0 0x100>;
180 reg = <0x100000 0x100>;
189 reg = <0x200000 0x100>;
198 reg = <0x300000 0x100>;
207 reg = <0x400000 0x100>;
217 #clock-cells = <0>;
224 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;