Lines Matching +full:0 +full:x1020
39 { 249600000, 2000000000, 0 },
44 .l = 0x20,
45 .alpha = 0x800,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329a299c,
49 .user_ctl_val = 0x00000001,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
72 { P_BI_TCXO, 0 },
82 { P_BI_TCXO, 0 },
96 { P_BI_TCXO, 0 },
106 { P_BI_TCXO, 0 },
116 { P_BI_TCXO, 0 },
124 F(19200000, P_BI_TCXO, 1, 0, 0),
125 F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
126 F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
131 .cmd_rcgr = 0x115c,
132 .mnd_width = 0,
145 .cmd_rcgr = 0x10c4,
146 .mnd_width = 0,
159 F(19200000, P_BI_TCXO, 1, 0, 0),
164 .cmd_rcgr = 0x10e0,
165 .mnd_width = 0,
178 F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
179 F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
180 F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
181 F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
182 F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
187 .cmd_rcgr = 0x107c,
188 .mnd_width = 0,
202 .cmd_rcgr = 0x1064,
216 F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
217 F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
222 .cmd_rcgr = 0x1094,
223 .mnd_width = 0,
236 .cmd_rcgr = 0x10ac,
237 .mnd_width = 0,
250 .reg = 0x10dc,
251 .shift = 0,
264 .halt_reg = 0x104c,
267 .enable_reg = 0x104c,
268 .enable_mask = BIT(0),
282 .halt_reg = 0x102c,
285 .enable_reg = 0x102c,
286 .enable_mask = BIT(0),
300 .halt_reg = 0x1030,
303 .enable_reg = 0x1030,
304 .enable_mask = BIT(0),
318 .halt_reg = 0x1034,
321 .enable_reg = 0x1034,
322 .enable_mask = BIT(0),
336 .halt_reg = 0x1010,
339 .enable_reg = 0x1010,
340 .enable_mask = BIT(0),
354 .halt_reg = 0x1020,
357 .enable_reg = 0x1020,
358 .enable_mask = BIT(0),
372 .halt_reg = 0x2004,
375 .enable_reg = 0x2004,
376 .enable_mask = BIT(0),
390 .halt_reg = 0x1168,
393 .enable_reg = 0x1168,
394 .enable_mask = BIT(0),
408 .halt_reg = 0x1018,
411 .enable_reg = 0x1018,
412 .enable_mask = BIT(0),
426 .halt_reg = 0x200c,
429 .enable_reg = 0x200c,
430 .enable_mask = BIT(0),
444 .halt_reg = 0x2008,
447 .enable_reg = 0x2008,
448 .enable_mask = BIT(0),
462 .halt_reg = 0x1028,
465 .enable_reg = 0x1028,
466 .enable_mask = BIT(0),
482 .enable_reg = 0x5004,
483 .enable_mask = BIT(0),
495 .enable_reg = 0x5008,
496 .enable_mask = BIT(0),
506 .gdscr = 0x1004,
507 .en_rest_wait_val = 0x2,
508 .en_few_wait_val = 0x2,
509 .clk_dis_wait_val = 0xf,
544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
545 [DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
556 .max_register = 0x10000,