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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
113 (0x0e00 << 16) | (0xc12c >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc140 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc150 >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc15c >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc168 >> 2),
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dcik.c150 * Returns 0 for success or -EINVAL for an invalid register
170 return 0; in cik_get_allowed_info_register()
205 int actual_temp = 0; in ci_get_temp()
210 if (temp & 0x200) in ci_get_temp()
213 actual_temp = temp & 0x1ff; in ci_get_temp()
222 int actual_temp = 0; in kv_get_temp()
224 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
229 actual_temp = 0; in kv_get_temp()
264 (0x0e00 << 16) | (0xc12c >> 2),
265 0x00000000,
[all …]
/linux-6.12.1/arch/s390/include/asm/
Dlowcore.h22 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
31 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
32 __u32 ipl_parmblock_ptr; /* 0x0014 */
33 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
34 __u32 ext_params; /* 0x0080 */
37 __u16 ext_cpu_addr; /* 0x0084 */
38 __u16 ext_int_code; /* 0x0086 */
42 __u32 svc_int_code; /* 0x0088 */
45 __u16 pgm_ilc; /* 0x008c */
46 __u16 pgm_code; /* 0x008e */
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/linux-6.12.1/drivers/tty/serial/
Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmcfdma.h21 #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
22 #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
24 #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
25 #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
27 #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
28 #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
33 #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
34 #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
35 #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
36 #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
[all …]
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
Dprcm-common.h22 #define OCP_MOD 0x000
23 #define MPU_MOD 0x100
24 #define CORE_MOD 0x200
25 #define GFX_MOD 0x300
26 #define WKUP_MOD 0x400
27 #define PLL_MOD 0x500
32 #define OMAP24XX_DSP_MOD 0x800
34 #define OMAP2430_MDM_MOD 0xc00
37 #define OMAP3430_IVA2_MOD -0x800
40 #define OMAP3430_DSS_MOD 0x600
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/linux-6.12.1/drivers/edac/
Dfsl_ddr_edac.h24 #define FSL_MC_DDR_SDRAM_CFG 0x0110
25 #define FSL_MC_CS_BNDS_0 0x0000
26 #define FSL_MC_CS_BNDS_OFS 0x0008
28 #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
29 #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
30 #define FSL_MC_ECC_ERR_INJECT 0x0e08
31 #define FSL_MC_CAPTURE_DATA_HI 0x0e20
32 #define FSL_MC_CAPTURE_DATA_LO 0x0e24
33 #define FSL_MC_CAPTURE_ECC 0x0e28
34 #define FSL_MC_ERR_DETECT 0x0e40
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Drcar-gen4-pci-ep.yaml100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
103 <0 0xfe000000 0 0x400000>;
Drcar-gen4-pci-host.yaml98 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
99 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
100 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
101 <0 0xfe000000 0 0x400000>;
117 bus-range = <0x00 0xff>;
119 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
120 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
121 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.12.1/drivers/misc/
Dtifm_7xx1.c15 #define TIFM_IRQ_ENABLE 0x80000000
19 #define TIFM_IRQ_SETALL 0xffffffff
44 if (irq_status == 0 || irq_status == (~0)) { in tifm_7xx1_isr()
52 for (cnt = 0; cnt < fm->num_sockets; cnt++) { in tifm_7xx1_isr()
83 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_toggle_sock_power()
95 return 0; in tifm_7xx1_toggle_sock_power()
105 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, in tifm_7xx1_toggle_sock_power()
147 fm->socket_change_set = 0; in tifm_7xx1_switch_media()
157 for (cnt = 0; cnt < fm->num_sockets; cnt++) { in tifm_7xx1_switch_media()
171 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_switch_media()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/
Dgate.txt31 - #clock-cells : from common clock binding; shall be set to 0
45 #clock-cells = <0>;
48 reg = <0x0a00>;
53 #clock-cells = <0>;
56 reg = <0x0a00>;
61 #clock-cells = <0>;
64 reg = <0x0e00>;
65 ti,bit-shift = <0>;
69 #clock-cells = <0>;
72 reg = <0x059c>;
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dcopypage_power7.S14 * instructions. We use a stream ID of 0 for the load side and
22 lis r7,0x0E01 /* depth=7
25 lis r7,0x0E00 /* depth=7 */
26 ori r7,r7,0x1000 /* units/cachelines=32 */
39 cmpwi r3,0
61 1: lvx v7,0,r4
70 stvx v7,0,r3
99 1: ld r0,0(r4)
116 std r0,0(r3)
/linux-6.12.1/include/linux/mfd/wm8350/
Daudio.h13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
/linux-6.12.1/drivers/net/dsa/mv88e6xxx/
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/linux-6.12.1/drivers/net/can/softing/
Dsofting.h105 #define DPRAM_RX 0x0000
108 #define DPRAM_RX_RD 0x0201 /* uint8_t */
109 #define DPRAM_RX_WR 0x0205 /* uint8_t */
110 #define DPRAM_RX_LOST 0x0207 /* uint8_t */
112 #define DPRAM_FCT_PARAM 0x0300 /* int16_t [20] */
113 #define DPRAM_FCT_RESULT 0x0328 /* int16_t */
114 #define DPRAM_FCT_HOST 0x032b /* uint16_t */
116 #define DPRAM_INFO_BUSSTATE 0x0331 /* uint16_t */
117 #define DPRAM_INFO_BUSSTATE2 0x0335 /* uint16_t */
118 #define DPRAM_INFO_ERRSTATE 0x0339 /* uint16_t */
[all …]
/linux-6.12.1/sound/pci/cs46xx/
Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]
/linux-6.12.1/drivers/net/phy/
Dqt2025.rs40 const PHY_DEVICE_ID: phy::DeviceId = phy::DeviceId::new_with_exact_mask(0x0043a400);
44 // Only 0x3b works with this driver and firmware. in probe()
45 let hw_rev = dev.read(C45::new(Mmd::PMAPMD, 0xd001))?; in probe()
46 if (hw_rev >> 8) != 0xb3 { in probe()
51 dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0000)?; in probe()
53 dev.write(C45::new(Mmd::PMAPMD, 0xc302), 0x0004)?; in probe()
55 dev.write(C45::new(Mmd::PMAPMD, 0xc319), 0x0038)?; in probe()
57 dev.write(C45::new(Mmd::PMAPMD, 0xc31a), 0x0098)?; in probe()
61 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
[all …]
/linux-6.12.1/drivers/block/
Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/linux-6.12.1/include/uapi/linux/
Din6.h83 #define IPV6_FL_A_GET 0
92 #define IPV6_FL_S_NONE 0
107 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
108 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
111 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
112 #define IPV6_PRIORITY_FILLER 0x0100
113 #define IPV6_PRIORITY_UNATTENDED 0x0200
114 #define IPV6_PRIORITY_RESERVED1 0x0300
115 #define IPV6_PRIORITY_BULK 0x0400
116 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
/linux-6.12.1/drivers/pcmcia/
Dtcic.h33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]

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