Lines Matching +full:0 +full:x0e00

105 #define DPRAM_RX		0x0000
108 #define DPRAM_RX_RD		0x0201	/* uint8_t */
109 #define DPRAM_RX_WR		0x0205	/* uint8_t */
110 #define DPRAM_RX_LOST		0x0207	/* uint8_t */
112 #define DPRAM_FCT_PARAM		0x0300	/* int16_t [20] */
113 #define DPRAM_FCT_RESULT	0x0328	/* int16_t */
114 #define DPRAM_FCT_HOST		0x032b	/* uint16_t */
116 #define DPRAM_INFO_BUSSTATE	0x0331	/* uint16_t */
117 #define DPRAM_INFO_BUSSTATE2	0x0335	/* uint16_t */
118 #define DPRAM_INFO_ERRSTATE	0x0339	/* uint16_t */
119 #define DPRAM_INFO_ERRSTATE2	0x033d	/* uint16_t */
120 #define DPRAM_RESET		0x0341	/* uint16_t */
121 #define DPRAM_CLR_RECV_FIFO	0x0345	/* uint16_t */
122 #define DPRAM_RESET_TIME	0x034d	/* uint16_t */
123 #define DPRAM_TIME		0x0350	/* uint64_t */
124 #define DPRAM_WR_START		0x0358	/* uint8_t */
125 #define DPRAM_WR_END		0x0359	/* uint8_t */
126 #define DPRAM_RESET_RX_FIFO	0x0361	/* uint16_t */
127 #define DPRAM_RESET_TX_FIFO	0x0364	/* uint8_t */
128 #define DPRAM_READ_FIFO_LEVEL	0x0365	/* uint8_t */
129 #define DPRAM_RX_FIFO_LEVEL	0x0366	/* uint16_t */
130 #define DPRAM_TX_FIFO_LEVEL	0x0366	/* uint16_t */
132 #define DPRAM_TX		0x0400	/* uint16_t */
135 #define DPRAM_TX_RD		0x0601	/* uint8_t */
136 #define DPRAM_TX_WR		0x0605	/* uint8_t */
138 #define DPRAM_COMMAND		0x07e0	/* uint16_t */
139 #define DPRAM_RECEIPT		0x07f0	/* uint16_t */
140 #define DPRAM_IRQ_TOHOST	0x07fe	/* uint8_t */
141 #define DPRAM_IRQ_TOCARD	0x07ff	/* uint8_t */
143 #define DPRAM_V2_RESET		0x0e00	/* uint8_t */
144 #define DPRAM_V2_IRQ_TOHOST	0x0e02	/* uint8_t */
149 #define RES_NONE	0
154 #define CMD_TX		0x01
155 #define CMD_ACK		0x02
156 #define CMD_XTD		0x04
157 #define CMD_RTR		0x08
158 #define CMD_ERR		0x10
159 #define CMD_BUS2	0x80
162 #define SF_MASK_BUSOFF		0x80
163 #define SF_MASK_EPASSIVE	0x60
168 #define STATE_EACTIVE	0