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/linux-6.12.1/drivers/media/usb/gspca/
Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dwlf,wm8903.yaml48 default: 0
63 If any entry has the value 0xffffffff, that GPIO's
91 #size-cells = <0>;
95 reg = <0x1a>;
106 micdet-cfg = <0>;
109 0x0600 /* DMIC_LR, output */
110 0x0680 /* DMIC_DAT, input */
111 0x0000 /* GPIO, output, low */
112 0x0200 /* Interrupt, output */
113 0x01a0 /* BCLK, input, active high */
/linux-6.12.1/drivers/gpu/drm/i915/soc/
Dintel_pch.h19 PCH_NONE = 0, /* No PCH present */
36 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
37 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
38 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
39 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
40 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
41 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
42 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
43 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
44 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
[all …]
/linux-6.12.1/drivers/video/fbdev/kyro/
DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-usb2.c3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
43 PHY_STATE_HS_ONLINE = 0,
62 USB_CHG_STATE_UNDEFINED = 0,
228 * struct rockchip_usb2phy - usb2.0 phy driver data.
310 return 0; in rockchip_usb2phy_reset()
330 return 0; in rockchip_usb2phy_clk480m_prepare()
380 int ret = 0; in rockchip_usb2phy_clk480m_register()
382 init.flags = 0; in rockchip_usb2phy_clk480m_register()
395 init.num_parents = 0; in rockchip_usb2phy_clk480m_register()
408 if (ret < 0) in rockchip_usb2phy_clk480m_register()
[all …]
/linux-6.12.1/sound/pci/cs46xx/
Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]
/linux-6.12.1/drivers/gpu/drm/etnaviv/
Detnaviv_cmd_parser.c28 ST(0x1200, 1),
29 ST(0x1228, 1),
30 ST(0x1238, 1),
31 ST(0x1284, 1),
32 ST(0x128c, 1),
33 ST(0x1304, 1),
34 ST(0x1310, 1),
35 ST(0x1318, 1),
36 ST(0x12800, 4),
37 ST(0x128a0, 4),
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-clps711x.c19 #define CLPS711X_INTSR1 (0x0240)
20 #define CLPS711X_INTMR1 (0x0280)
21 #define CLPS711X_BLEOI (0x0600)
22 #define CLPS711X_MCEOI (0x0640)
23 #define CLPS711X_TEOI (0x0680)
24 #define CLPS711X_TC1EOI (0x06c0)
25 #define CLPS711X_TC2EOI (0x0700)
26 #define CLPS711X_RTCEOI (0x0740)
27 #define CLPS711X_UMSEOI (0x0780)
28 #define CLPS711X_COEOI (0x07c0)
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/igbvf/
Digbvf.h28 lowest_latency = 0,
35 #define IGBVF_INT_MODE_LEGACY 0
54 * Setting this to 0 disables RX descriptor prefetch.
57 * If PTHRESH is 0, this should also be 0.
66 /* this is the size past which hardware will drop packets when setting LPE=0 */
69 #define IGBVF_FC_PAUSE_TIME 0x0680 /* 858 usec */
76 #define AUTO_ALL_MODES 0
77 #define IGBVF_EEPROM_APME 0x0400
268 #define IGBVF_FLAG_RX_CSUM_DISABLED BIT(0)
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv25.c36 NVKM_MEM_TARGET_INST, 0x3724, 16, true, in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); in nv25_gr_chan_new()
[all …]
Dnv30.c37 NVKM_MEM_TARGET_INST, 0x5f48, 16, true, in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
[all …]
/linux-6.12.1/arch/parisc/include/asm/
Dropes.h47 #if DELAYED_RESOURCE_CNT > 0
56 #define SBA_SEARCH_SAMPLE 0x100
92 #define ASTRO_RUNWAY_PORT 0x582
93 #define IKE_MERCED_PORT 0x803
94 #define REO_MERCED_PORT 0x804
95 #define REOG_MERCED_PORT 0x805
96 #define PLUTO_MCKINLEY_PORT 0x880
114 #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
116 #define SBA_AGPGART_COOKIE (__force __le64) 0x0000badbadc0ffeeULL
118 #define SBA_FUNC_ID 0x0000 /* function id */
[all …]
/linux-6.12.1/drivers/net/ethernet/renesas/
Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux-6.12.1/include/linux/mfd/
Dmotorola-cpcap.h17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/e1000e/
De1000.h42 #define E1000E_INT_MODE_LEGACY 0
58 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
64 #define AUTO_ALL_MODES 0
65 #define E1000_EEPROM_APME 0x0400
79 #define PCICFG_DESC_RING_STATUS 0xe4
80 #define FLUSH_DESC_REQUIRED 0x100
92 0x1f) /* pthresh */
95 (0x01000000 | /* set descriptor granularity */ \
98 0x20) /* set hthresh */
355 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtl818x/rtl8180/
Drtl8225se.c24 0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
25 0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
26 0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
27 0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
28 0x0183, 0x0163, 0x0143, 0x0123, 0x0103
32 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
33 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
34 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
35 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
36 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
[all …]
/linux-6.12.1/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h12 /* 0x0000h ~ 0x00FFh System Configuration */
15 #define REG_SYS_FUNC_EN 0x0002
16 #define REG_APS_FSMCO 0x0004
17 #define REG_SYS_CLKR 0x0008
18 #define REG_9346CR 0x000A
19 #define REG_SYS_EEPROM_CTRL 0x000A
20 #define REG_RSV_CTRL 0x001C
21 #define REG_RF_CTRL 0x001F
22 #define REG_AFE_XTAL_CTRL 0x0024
23 #define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtl818x/rtl8187/
Drtl8225.c28 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread8_idx()
30 (unsigned long)addr, idx & 0x03, in rtl818x_ioread8_idx()
45 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread16_idx()
47 (unsigned long)addr, idx & 0x03, in rtl818x_ioread16_idx()
62 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread32_idx()
64 (unsigned long)addr, idx & 0x03, in rtl818x_ioread32_idx()
79 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite8_idx()
81 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite8_idx()
93 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite16_idx()
95 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite16_idx()
[all …]
/linux-6.12.1/include/video/
Dmach64.h20 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21 #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23 #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
24 #define CRTC_H_SYNC_STRT 0x0004
25 #define CRTC2_H_SYNC_STRT 0x0004
26 #define CRTC_H_SYNC_DLY 0x0005
27 #define CRTC2_H_SYNC_DLY 0x0005
28 #define CRTC_H_SYNC_WID 0x0006
29 #define CRTC2_H_SYNC_WID 0x0006
[all …]
/linux-6.12.1/arch/powerpc/sysdev/
Dfsl_rio.c42 #define RIO_PORT1_EDCSR 0x0640
43 #define RIO_PORT2_EDCSR 0x0680
44 #define RIO_PORT1_IECSR 0x10130
45 #define RIO_PORT2_IECSR 0x101B0
47 #define RIO_GCCSR 0x13c
48 #define RIO_ESCSR 0x158
49 #define ESCSR_CLEAR 0x07120204
50 #define RIO_PORT2_ESCSR 0x178
51 #define RIO_CCSR 0x15c
52 #define RIO_LTLEDCSR_IER 0x80000000
[all …]
/linux-6.12.1/drivers/media/pci/solo6x10/
Dsolo6x10-regs.h20 #define SOLO_SYS_CFG 0x0000
21 #define SOLO_SYS_CFG_FOUT_EN 0x00000001
22 #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002
23 #define SOLO_SYS_CFG_PLL_PWDN 0x00000004
24 #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3)
25 #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5)
26 #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14)
27 #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000
28 #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24)
29 #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26)
[all …]

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