37 			      NVKM_MEM_TARGET_INST, 0x5f48, 16, true,  in nv30_gr_chan_new()
43 	nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));  in nv30_gr_chan_new()
44 	nvkm_wo32(chan->inst, 0x0410, 0x00000101);  in nv30_gr_chan_new()
45 	nvkm_wo32(chan->inst, 0x0424, 0x00000111);  in nv30_gr_chan_new()
46 	nvkm_wo32(chan->inst, 0x0428, 0x00000060);  in nv30_gr_chan_new()
47 	nvkm_wo32(chan->inst, 0x0444, 0x00000080);  in nv30_gr_chan_new()
48 	nvkm_wo32(chan->inst, 0x0448, 0xffff0000);  in nv30_gr_chan_new()
49 	nvkm_wo32(chan->inst, 0x044c, 0x00000001);  in nv30_gr_chan_new()
50 	nvkm_wo32(chan->inst, 0x0460, 0x44400000);  in nv30_gr_chan_new()
51 	nvkm_wo32(chan->inst, 0x048c, 0xffff0000);  in nv30_gr_chan_new()
52 	for (i = 0x04e0; i < 0x04e8; i += 4)  in nv30_gr_chan_new()
53 		nvkm_wo32(chan->inst, i, 0x0fff0000);  in nv30_gr_chan_new()
54 	nvkm_wo32(chan->inst, 0x04ec, 0x00011100);  in nv30_gr_chan_new()
55 	for (i = 0x0508; i < 0x0548; i += 4)  in nv30_gr_chan_new()
56 		nvkm_wo32(chan->inst, i, 0x07ff0000);  in nv30_gr_chan_new()
57 	nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff);  in nv30_gr_chan_new()
58 	nvkm_wo32(chan->inst, 0x058c, 0x00000080);  in nv30_gr_chan_new()
59 	nvkm_wo32(chan->inst, 0x0590, 0x30201000);  in nv30_gr_chan_new()
60 	nvkm_wo32(chan->inst, 0x0594, 0x70605040);  in nv30_gr_chan_new()
61 	nvkm_wo32(chan->inst, 0x0598, 0xb8a89888);  in nv30_gr_chan_new()
62 	nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8);  in nv30_gr_chan_new()
63 	nvkm_wo32(chan->inst, 0x05b0, 0xb0000000);  in nv30_gr_chan_new()
64 	for (i = 0x0600; i < 0x0640; i += 4)  in nv30_gr_chan_new()
65 		nvkm_wo32(chan->inst, i, 0x00010588);  in nv30_gr_chan_new()
66 	for (i = 0x0640; i < 0x0680; i += 4)  in nv30_gr_chan_new()
67 		nvkm_wo32(chan->inst, i, 0x00030303);  in nv30_gr_chan_new()
68 	for (i = 0x06c0; i < 0x0700; i += 4)  in nv30_gr_chan_new()
69 		nvkm_wo32(chan->inst, i, 0x0008aae4);  in nv30_gr_chan_new()
70 	for (i = 0x0700; i < 0x0740; i += 4)  in nv30_gr_chan_new()
71 		nvkm_wo32(chan->inst, i, 0x01012000);  in nv30_gr_chan_new()
72 	for (i = 0x0740; i < 0x0780; i += 4)  in nv30_gr_chan_new()
73 		nvkm_wo32(chan->inst, i, 0x00080008);  in nv30_gr_chan_new()
74 	nvkm_wo32(chan->inst, 0x085c, 0x00040000);  in nv30_gr_chan_new()
75 	nvkm_wo32(chan->inst, 0x0860, 0x00010000);  in nv30_gr_chan_new()
76 	for (i = 0x0864; i < 0x0874; i += 4)  in nv30_gr_chan_new()
77 		nvkm_wo32(chan->inst, i, 0x00040004);  in nv30_gr_chan_new()
78 	for (i = 0x1f18; i <= 0x3088 ; i += 16) {  in nv30_gr_chan_new()
79 		nvkm_wo32(chan->inst, i + 0, 0x10700ff9);  in nv30_gr_chan_new()
80 		nvkm_wo32(chan->inst, i + 4, 0x0436086c);  in nv30_gr_chan_new()
81 		nvkm_wo32(chan->inst, i + 8, 0x000c001b);  in nv30_gr_chan_new()
83 	for (i = 0x30b8; i < 0x30c8; i += 4)  in nv30_gr_chan_new()
84 		nvkm_wo32(chan->inst, i, 0x0000ffff);  in nv30_gr_chan_new()
85 	nvkm_wo32(chan->inst, 0x344c, 0x3f800000);  in nv30_gr_chan_new()
86 	nvkm_wo32(chan->inst, 0x3808, 0x3f800000);  in nv30_gr_chan_new()
87 	nvkm_wo32(chan->inst, 0x381c, 0x3f800000);  in nv30_gr_chan_new()
88 	nvkm_wo32(chan->inst, 0x3848, 0x40000000);  in nv30_gr_chan_new()
89 	nvkm_wo32(chan->inst, 0x384c, 0x3f800000);  in nv30_gr_chan_new()
90 	nvkm_wo32(chan->inst, 0x3850, 0x3f000000);  in nv30_gr_chan_new()
91 	nvkm_wo32(chan->inst, 0x3858, 0x40000000);  in nv30_gr_chan_new()
92 	nvkm_wo32(chan->inst, 0x385c, 0x3f800000);  in nv30_gr_chan_new()
93 	nvkm_wo32(chan->inst, 0x3864, 0xbf800000);  in nv30_gr_chan_new()
94 	nvkm_wo32(chan->inst, 0x386c, 0xbf800000);  in nv30_gr_chan_new()
96 	return 0;  in nv30_gr_chan_new()
112 	nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);  in nv30_gr_init()
113 	nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);  in nv30_gr_init()
115 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);  in nv30_gr_init()
116 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);  in nv30_gr_init()
117 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);  in nv30_gr_init()
118 	nvkm_wr32(device, 0x400890, 0x01b463ff);  in nv30_gr_init()
119 	nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475);  in nv30_gr_init()
120 	nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);  in nv30_gr_init()
121 	nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);  in nv30_gr_init()
122 	nvkm_wr32(device, 0x400B80, 0x1003d888);  in nv30_gr_init()
123 	nvkm_wr32(device, 0x400B84, 0x0c000000);  in nv30_gr_init()
124 	nvkm_wr32(device, 0x400098, 0x00000000);  in nv30_gr_init()
125 	nvkm_wr32(device, 0x40009C, 0x0005ad00);  in nv30_gr_init()
126 	nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */  in nv30_gr_init()
127 	nvkm_wr32(device, 0x4000a0, 0x00000000);  in nv30_gr_init()
128 	nvkm_wr32(device, 0x4000a4, 0x00000008);  in nv30_gr_init()
129 	nvkm_wr32(device, 0x4008a8, 0xb784a400);  in nv30_gr_init()
130 	nvkm_wr32(device, 0x400ba0, 0x002f8685);  in nv30_gr_init()
131 	nvkm_wr32(device, 0x400ba4, 0x00231f3f);  in nv30_gr_init()
132 	nvkm_wr32(device, 0x4008a4, 0x40000020);  in nv30_gr_init()
134 	if (device->chipset == 0x34) {  in nv30_gr_init()
135 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);  in nv30_gr_init()
136 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201);  in nv30_gr_init()
137 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);  in nv30_gr_init()
138 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008);  in nv30_gr_init()
139 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);  in nv30_gr_init()
140 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032);  in nv30_gr_init()
141 		nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004);  in nv30_gr_init()
142 		nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002);  in nv30_gr_init()
145 	nvkm_wr32(device, 0x4000c0, 0x00000016);  in nv30_gr_init()
147 	nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);  in nv30_gr_init()
148 	nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);  in nv30_gr_init()
149 	nvkm_wr32(device, 0x0040075c             , 0x00000001);  in nv30_gr_init()
153 	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));  in nv30_gr_init()
154 	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));  in nv30_gr_init()
155 	if (device->chipset != 0x34) {  in nv30_gr_init()
156 		nvkm_wr32(device, 0x400750, 0x00EA0000);  in nv30_gr_init()
157 		nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200));  in nv30_gr_init()
158 		nvkm_wr32(device, 0x400750, 0x00EA0004);  in nv30_gr_init()
159 		nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204));  in nv30_gr_init()
162 	return 0;  in nv30_gr_init()
174 		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
175 		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
176 		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
177 		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
178 		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
179 		{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
180 		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
181 		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
182 		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
183 		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
184 		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
185 		{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
186 		{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
187 		{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
188 		{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
189 		{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
190 		{ -1, -1, 0x0397, &nv04_gr_object }, /* rankine */
191 		{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */