42 #define RIO_PORT1_EDCSR		0x0640
43 #define RIO_PORT2_EDCSR		0x0680
44 #define RIO_PORT1_IECSR		0x10130
45 #define RIO_PORT2_IECSR		0x101B0
47 #define RIO_GCCSR		0x13c
48 #define RIO_ESCSR		0x158
49 #define ESCSR_CLEAR		0x07120204
50 #define RIO_PORT2_ESCSR		0x178
51 #define RIO_CCSR		0x15c
52 #define RIO_LTLEDCSR_IER	0x80000000
53 #define RIO_LTLEDCSR_PRT	0x01000000
54 #define IECSR_CLEAR		0x80000000
55 #define RIO_ISR_AACR		0x10120
56 #define RIO_ISR_AACR_AA		0x1	/* Accept All ID */
59 #define RIWTAR_TRAD_MASK	0x00FFFFFF
61 #define RIWBAR_BADD_MASK	0x003FFFFF
62 #define RIWAR_ENABLE		0x80000000
63 #define RIWAR_TGINT_LOCAL	0x00F00000
64 #define RIWAR_RDTYP_NO_SNOOP	0x00040000
65 #define RIWAR_RDTYP_SNOOP	0x00050000
66 #define RIWAR_WRTYP_NO_SNOOP	0x00004000
67 #define RIWAR_WRTYP_SNOOP	0x00005000
68 #define RIWAR_WRTYP_ALLOC	0x00006000
69 #define RIWAR_SIZE_MASK		0x0000003F
75 		"1:	"op" %1,0(%2)\n"		\
80 		"	li %0,%3\n"			\
85 		: "b" (addr), "i" (-EFAULT), "0" (err))
109 		return 0;  in fsl_rio_mcheck_exception()
119 				 0);  in fsl_rio_mcheck_exception()
126 	return 0;  in fsl_rio_mcheck_exception()
139  * Generates a MPC85xx local configuration space read. Returns %0 on
150 	return 0;  in fsl_local_config_read()
161  * Generates a MPC85xx local configuration space write. Returns %0 on
173 	return 0;  in fsl_local_config_write()
186  * Generates a MPC85xx read maintenance transaction. Returns %0 on
196 	u32 rval, err = 0;  in fsl_rio_config_read()
205 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))  in fsl_rio_config_read()
251  * Generates an MPC85xx write maintenance transaction. Returns %0 on
261 	int ret = 0;  in fsl_rio_config_write()
270 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))  in fsl_rio_config_write()
303 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++)  in fsl_rio_inbound_mem_init()
304 		out_be32(&priv->inb_atmu_regs[i].riwar, 0);  in fsl_rio_inbound_mem_init()
317 	if ((size & (size - 1)) != 0 || size > 0x400000000ULL)  in fsl_map_inb_mem()
330 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {  in fsl_map_inb_mem()
332 		if ((riwar & RIWAR_ENABLE) == 0)  in fsl_map_inb_mem()
342 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {  in fsl_map_inb_mem()
344 		if ((riwar & RIWAR_ENABLE) == 0)  in fsl_map_inb_mem()
355 	return 0;  in fsl_map_inb_mem()
367 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {  in fsl_unmap_inb_mem()
369 		if ((riwar & RIWAR_ENABLE) == 0)  in fsl_unmap_inb_mem()
384 	out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);  in fsl_rio_port_error_handler()
386 	if (offset == 0) {  in fsl_rio_port_error_handler()
387 		out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);  in fsl_rio_port_error_handler()
391 		out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);  in fsl_rio_port_error_handler()
402 		case 0:  in fsl_rio_info()
415 		case 0:  in fsl_rio_info()
416 			str = "Single-lane 0";  in fsl_rio_info()
431 		if (!(ccsr & 0x80000000))  in fsl_rio_info()
433 		if (!(ccsr & 0x08000000))  in fsl_rio_info()
451 	int rc = 0;  in fsl_rio_setup()
453 	u32 active_ports = 0;  in fsl_rio_setup()
466 	rio_regs_win = of_iomap(dev->dev.of_node, 0);  in fsl_rio_setup()
494 	rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);  in fsl_rio_setup()
500 	rmu_regs_win = of_iomap(rmu_node, 0);  in fsl_rio_setup()
530 	if (of_property_read_reg(np, 0, &range_start, NULL)) {  in fsl_rio_setup()
553 	pw->pwirq = irq_of_parse_and_map(np, 0);  in fsl_rio_setup()
555 	if (of_property_read_reg(np, 0, &range_start, NULL)) {  in fsl_rio_setup()
574 		if (of_range_to_resource(np, 0, &res)) {  in fsl_rio_setup()
607 		if (request_resource(&iomem_resource, &port->iores) < 0) {  in fsl_rio_setup()
609 				" 0x%016llx-0x%016llx\n",  in fsl_rio_setup()
621 		port->phys_efptr = 0x100;  in fsl_rio_setup()
625 		ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);  in fsl_rio_setup()
628 		if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {  in fsl_rio_setup()
633 				+ RIO_CCSR + i*0x20, 0);  in fsl_rio_setup()
636 				+ RIO_CCSR + i*0x20, 0x02000000);  in fsl_rio_setup()
639 				+ RIO_CCSR + i*0x20, 0x00600000);  in fsl_rio_setup()
642 					+ RIO_ESCSR + i*0x20)) & 1) {  in fsl_rio_setup()
659 		if (port->host_deviceid >= 0)  in fsl_rio_setup()
667 			+ ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :  in fsl_rio_setup()
673 			((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :  in fsl_rio_setup()
677 		out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),  in fsl_rio_setup()
684 			 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));  in fsl_rio_setup()
714 	return 0;  in fsl_rio_setup()