qcacmn: assign dump functions to per chip specific1. add more function pointers for the remainder functions which aregeneric2. assign functions to per chip level3. prevent using generic rx_pkt_t
qcacmn: assign dump functions to per chip specific1. add more function pointers for the remainder functions which aregeneric2. assign functions to per chip level3. prevent using generic rx_pkt_tlv struct and using at a per socspecific insteadChange-Id: I1cefb10c7a70f04dbf8b110fcfee6f1c9f4ab1a0CRs-Fixed: 3533521
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qcacmn: qcacmn: Add Monitor 1.0 support for WCN6450Currently in monitor mode, links are released to WBM through theSW2WBM_RELEASE ring and WBM will feed the links back to RXDMAthrough the WBM2RXD
qcacmn: qcacmn: Add Monitor 1.0 support for WCN6450Currently in monitor mode, links are released to WBM through theSW2WBM_RELEASE ring and WBM will feed the links back to RXDMAthrough the WBM2RXDMA_LINK_RING.WCN6450 uses SOFTUMAC architecture where WBM is not present.Hence the WBM2RXDMA_LINK_RING is repurposed to SW2RXDMA_LINK_RINGwhere host will directly release the links to RXDMA using this ring.Change-Id: I110f607e38c4c2ab10eb1bd7b1f5a7bce2f03692CRs-Fixed: 3493368
qcacmn: Fix typographical errorsFix typographical errors spanned over various files in cmn.Change-Id: I9fcf3b7f9bb7d7dd406e6576a60aa4eb783c9cebCRs-Fixed: 3529628
qcacmn: Remove trailing newline from the DP LogsRemove trailing newline from the DP Logs.Change-Id: Iaf54e57fb44cf7c15d82bd5c0ffb3fc7c3d04a2bCRs-Fixed: 3492501
qcacmn: Fix hal/wifi3.0/qca6290 documentationThe kernel-doc script identified some documentation issues in thehal/wifi3.0/qca6290 folder, so fix them.Change-Id: I5b5943039d62a60f71faf322cf66fe41
qcacmn: Fix hal/wifi3.0/qca6290 documentationThe kernel-doc script identified some documentation issues in thehal/wifi3.0/qca6290 folder, so fix them.Change-Id: I5b5943039d62a60f71faf322cf66fe411c11b3deCRs-Fixed: 3406597
qcacmn: hal: Fix misspellingsFix misspellings in hal/...Change-Id: Icf033a647e6a15d46420d7102dc161b94fa7dd2cCRs-Fixed: 3304685
qcacmn: Separate GetFrameControl API's for LI chipsetsFor 802.11 Fragmented frames, currently there is ageneric GetFrameControl API from RX TLV for all LiChipsets. As the offset for frame control
qcacmn: Separate GetFrameControl API's for LI chipsetsFor 802.11 Fragmented frames, currently there is ageneric GetFrameControl API from RX TLV for all LiChipsets. As the offset for frame control in RX TLVis different for QCN9000 and QCA8074V2, reading theframe control with generic API gives wrong framecontrol value. The Offset is different as the sizeof RX_MSDU_START struct is 8DWORDS in QCA8074v2 whileit is 9DWORDS in QCA9000. In the reo reinject paththe destination queue descriptor address read from ringdescriptor address is InvalidFix is Separating out the GetFrameControl API fromgeneric API to Chip specific API. Also fix the readingof queue descriptor address.CRs-Fixed: 3280809change-Id: Ifc5eca31b9b7e70c84ca455d56a58c27601cd51d
qcacmn: Get the peer meta data from msdu end tlvIn QCN9224 fetch the peer meta data from the msdu end tlvinstead of MPDU startChange-Id: Icd9420cd83e06abe5e54e9e05cc8cbf8d8312ae1CRs-Fixed: 3245
qcacmn: Get the peer meta data from msdu end tlvIn QCN9224 fetch the peer meta data from the msdu end tlvinstead of MPDU startChange-Id: Icd9420cd83e06abe5e54e9e05cc8cbf8d8312ae1CRs-Fixed: 3245626
qcacmn: Set default value for REO dest ctrl registerCurrently in some case we are receiving non error packets on REO2TCLring, which is causing issue.Fix is to set DEST_RING_MAPPING_0 to SW1 for
qcacmn: Set default value for REO dest ctrl registerCurrently in some case we are receiving non error packets on REO2TCLring, which is causing issue.Fix is to set DEST_RING_MAPPING_0 to SW1 for REO dest ctrlregister, So that non error packets with reo_destination_indicationwith 0x0 in the reo entrance ring will be routed to SW1 ring.Change-Id: I67f78f35e7dba899943307902d99d0325a60498fCRs-Fixed: 3150186
qcacmn: Mark first packet after wow wakeupAdd feature support to tag first packet that wakes up HOST from WoW.rx_pkt_tlv.rx_msdu_end.reserved_1a field is used by TARGET to meetsuch request.Cha
qcacmn: Mark first packet after wow wakeupAdd feature support to tag first packet that wakes up HOST from WoW.rx_pkt_tlv.rx_msdu_end.reserved_1a field is used by TARGET to meetsuch request.Change-Id: I3d37e13e8cff49bc4f622d3070a19e4c4be56417CRs-Fixed: 3137621
qcacmn: Move CCE and flow hal implementation to per chipMove CCE and flow hal implementation to per chip hal layer.Change-Id: I95a37d8bab00cdecfd6e8ae9a724b8c5541b336e
qcacmn: In WBM err process read peer_id from peer_meta_dataIn WBM error processing read peer_id from peer_meta_datainstead of sw_peer_id.This changes is needed because we need to process Rx pack
qcacmn: In WBM err process read peer_id from peer_meta_dataIn WBM error processing read peer_id from peer_meta_datainstead of sw_peer_id.This changes is needed because we need to process Rx packeton ML peer. But in MLO case sw_peer_id field containslink_peer_id where as peer_meta_data has ml_peer_id.Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
qcacmn: Add support for beryllium on WINAdd support for split between lithium and berylliumHAL files.Add Wkk TLV support.Change-Id: I7135e4061a4c3605d76c70c33320cbd533ea0c62
qcacmn: Use sw_peer_id instead of ast_index to get peerIn order to support flow overide feature,AST table has to be split between RxPCU and DDR.With this split, RX monitor cannot make use ofast_
qcacmn: Use sw_peer_id instead of ast_index to get peerIn order to support flow overide feature,AST table has to be split between RxPCU and DDR.With this split, RX monitor cannot make use ofast_index to fetch peer as it is not from DDR.So make use of sw_peer_id to fetch peer.This sw_peer_id is derived from RX_MPDU_STAT_START_TLVChange-Id: Ib2a003a2640fded3287c318d2ad59fd3127af9b6CRs-fixed: 3004363
qcacmn: Fix lithium HAL generic APIsHAL generic APIs which use HW definitons thatdo not have same value across all lithium chipsetare moved to header files. So that these will becompiled with ap
qcacmn: Fix lithium HAL generic APIsHAL generic APIs which use HW definitons thatdo not have same value across all lithium chipsetare moved to header files. So that these will becompiled with appropriate header filesChange-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
qcacmn: Move to index based assignment for srng register offsetCurrently the hardware srng register offset is staticallyassigned to the handle. This can lead to incorrect index accesswhen targets
qcacmn: Move to index based assignment for srng register offsetCurrently the hardware srng register offset is staticallyassigned to the handle. This can lead to incorrect index accesswhen targets (eg: wcn7850) is added which require additionalregister offsets to be stored in the hw srng register offset table.Move to the index based assignment of the srng register offset.Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8CRs-Fixed: 2965081
qcacmn: Add HAL APIs for Lithium targetsAdd hal soc API handlers for existing Lithium targets.Change-Id: I2ca25c94702759eb8329eb24048c9f5732caa3ccCRs-Fixed: 2891049
qcacmn: Use function to attach HAL TX/RX opsAssign th HAL TX/RX ops in a function instead of assining a structuredirectly. This can be later extended to have default ops for a family ofchips and
qcacmn: Use function to attach HAL TX/RX opsAssign th HAL TX/RX ops in a function instead of assining a structuredirectly. This can be later extended to have default ops for a family ofchips and then override that with chip specific ops.This also helps the case where a new hal_soc->ops needs to be added.The new 'op' will need to be added to only a default ops initializer(with assumption that it applies to all chips).Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6fCRs-Fixed: 2891049
qcacmn: Send ring sel cfg to configure rx pkt tlvs offsetCurrently the FW configures the mac with appropriateoffsets for rx pkt tlvs using the structure defined inte FW and the host does not send
qcacmn: Send ring sel cfg to configure rx pkt tlvs offsetCurrently the FW configures the mac with appropriateoffsets for rx pkt tlvs using the structure defined inte FW and the host does not send the ring selction configHTT message. This can create a problem when FW stops subscribingto tlvs or changes its rx pkt tlvs offset.Fix this by configuring the rx pkt tlv offsets via HTTring selection config message.Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0beeCRs-Fixed: 2860504
qcacmn: hal: Initialize hal_hw_txrx_ops for 6290Change hal_hw_txrx_ops struct to designated initializer syntax forstructs for 6290.Change-Id: I33f467b411c7695a838646bd7e370a75370b898cCRs-Fixed:
qcacmn: hal: Initialize hal_hw_txrx_ops for 6290Change hal_hw_txrx_ops struct to designated initializer syntax forstructs for 6290.Change-Id: I33f467b411c7695a838646bd7e370a75370b898cCRs-Fixed: 2837917
qcacmn: Stop FISA if frame rings mismatchIf frames from the same FISA flow goes into different REO2SW rings, itwill result in an unexpected FISA behavior. This can happen if theframes have been r
qcacmn: Stop FISA if frame rings mismatchIf frames from the same FISA flow goes into different REO2SW rings, itwill result in an unexpected FISA behavior. This can happen if theframes have been reinjected from FW offload module since FW will selectREO2SW1 ring. If the same flow frames hash to other REO2SW rings, thenthe same flow UDP frames will do to different rings.Reo_destination_indication of 6 indicates if the frame has beenreinjected from FW. If so, then continue to deliver the packet withoutFISA.Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70CRs-Fixed: 2790292
qcacmn: Update REO Remap config API as platform specificUpdate REO Remap config API as platform specificChange-Id: I6a38b87e9181e8bc939e49e3eb55fcd6cace626d
qcacmn: qcn9000 changes in rx flow identificationRx flow indentification changes to providesupport on Qcn9000 targetChange-Id: I1b7ef8c93e38e753cb7014dca68148a4174daa82
qcacmn: Get Rx TLV offsets from structureSize of the TLVs have changed across generation of chipsetsOffset values need to be configured into DMA register for preheader DMAAdded APIs to get offset
qcacmn: Get Rx TLV offsets from structureSize of the TLVs have changed across generation of chipsetsOffset values need to be configured into DMA register for preheader DMAAdded APIs to get offsets of each TLV based on chip typeChange-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
qcacmn: Support RX 2K jump/OOR frame handling from REO2TCL ringSupport RX 2K jump/OOR frame handling from REO2TCL ring.(a) configure REO error destination ring register to route 2K jump/OOR frame
qcacmn: Support RX 2K jump/OOR frame handling from REO2TCL ringSupport RX 2K jump/OOR frame handling from REO2TCL ring.(a) configure REO error destination ring register to route 2K jump/OOR frame to REO2TCL ring.(b) for 2K jump RX frame, only accept ARP frame and drop others,meanwhile, send delba action frame to remote peer once receive first2K jump data.(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwisedrop it.Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057CRs-Fixed: 2631949
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