1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * NB: Inappropriate references to "HTC" are used in this (and other) 22 * HIF implementations. HTC is typically the calling layer, but it 23 * theoretically could be some alternative. 24 */ 25 26 /* 27 * This holds all state needed to process a pending send/recv interrupt. 28 * The information is saved here as soon as the interrupt occurs (thus 29 * allowing the underlying CE to re-use the ring descriptor). The 30 * information here is eventually processed by a completion processing 31 * thread. 32 */ 33 34 #ifndef __HIF_MAIN_H__ 35 #define __HIF_MAIN_H__ 36 37 #include <qdf_atomic.h> /* qdf_atomic_read */ 38 #include "qdf_lock.h" 39 #include "cepci.h" 40 #include "hif.h" 41 #include "multibus.h" 42 #include "hif_unit_test_suspend_i.h" 43 #ifdef HIF_CE_LOG_INFO 44 #include "qdf_notifier.h" 45 #endif 46 #include "pld_common.h" 47 48 #define HIF_MIN_SLEEP_INACTIVITY_TIME_MS 50 49 #define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60 50 51 #define HIF_MAX_BUDGET 0xFFFF 52 53 #define HIF_STATS_INC(_handle, _field, _delta) \ 54 { \ 55 (_handle)->stats._field += _delta; \ 56 } 57 58 /* 59 * This macro implementation is exposed for efficiency only. 60 * The implementation may change and callers should 61 * consider the targid to be a completely opaque handle. 62 */ 63 #define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid))) 64 65 #ifdef QCA_WIFI_3_0 66 #define DISABLE_L1SS_STATES 1 67 #endif 68 69 #define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES 70 71 #ifdef QCA_WIFI_3_0_ADRASTEA 72 #define ADRASTEA_BU 1 73 #else 74 #define ADRASTEA_BU 0 75 #endif 76 77 #ifdef QCA_WIFI_3_0 78 #define HAS_FW_INDICATOR 0 79 #else 80 #define HAS_FW_INDICATOR 1 81 #endif 82 83 84 #define AR9888_DEVICE_ID (0x003c) 85 #define AR6320_DEVICE_ID (0x003e) 86 #define AR6320_FW_1_1 (0x11) 87 #define AR6320_FW_1_3 (0x13) 88 #define AR6320_FW_2_0 (0x20) 89 #define AR6320_FW_3_0 (0x30) 90 #define AR6320_FW_3_2 (0x32) 91 #define QCA6290_EMULATION_DEVICE_ID (0xabcd) 92 #define QCA6290_DEVICE_ID (0x1100) 93 #define QCN9000_DEVICE_ID (0x1104) 94 #define QCN9224_DEVICE_ID (0x1109) 95 #define QCN6122_DEVICE_ID (0xFFFB) 96 #define QCN9160_DEVICE_ID (0xFFF8) 97 #define QCN6432_DEVICE_ID (0xFFF7) 98 #define QCA6390_EMULATION_DEVICE_ID (0x0108) 99 #define QCA6390_DEVICE_ID (0x1101) 100 /* TODO: change IDs for HastingsPrime */ 101 #define QCA6490_EMULATION_DEVICE_ID (0x010a) 102 #define QCA6490_DEVICE_ID (0x1103) 103 #define MANGO_DEVICE_ID (0x110a) 104 #define PEACH_DEVICE_ID (0x110e) 105 106 /* TODO: change IDs for Moselle */ 107 #define QCA6750_EMULATION_DEVICE_ID (0x010c) 108 #define QCA6750_DEVICE_ID (0x1105) 109 110 /* TODO: change IDs for Hamilton */ 111 #define KIWI_DEVICE_ID (0x1107) 112 113 /*TODO: change IDs for Evros */ 114 #define WCN6450_DEVICE_ID (0x1108) 115 116 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021) 117 #define AR9887_DEVICE_ID (0x0050) 118 #define AR900B_DEVICE_ID (0x0040) 119 #define QCA9984_DEVICE_ID (0x0046) 120 #define QCA9888_DEVICE_ID (0x0056) 121 #define QCA8074_DEVICE_ID (0xffff) /* Todo: replace this with 122 actual number once available. 123 currently defining this to 0xffff for 124 emulation purpose */ 125 #define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */ 126 #define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */ 127 #define QCA5018_DEVICE_ID (0xfffc) /* Todo: replace this with actual number */ 128 #define QCA9574_DEVICE_ID (0xfffa) 129 #define QCA5332_DEVICE_ID (0xfff9) 130 /* Genoa */ 131 #define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/ 132 #define QCN7605_COMPOSITE (0x9901) 133 #define QCN7605_STANDALONE (0x9900) 134 #define QCN7605_STANDALONE_V2 (0x9902) 135 #define QCN7605_COMPOSITE_V2 (0x9903) 136 137 #define RUMIM2M_DEVICE_ID_NODE0 0xabc0 138 #define RUMIM2M_DEVICE_ID_NODE1 0xabc1 139 #define RUMIM2M_DEVICE_ID_NODE2 0xabc2 140 #define RUMIM2M_DEVICE_ID_NODE3 0xabc3 141 #define RUMIM2M_DEVICE_ID_NODE4 0xaa10 142 #define RUMIM2M_DEVICE_ID_NODE5 0xaa11 143 144 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn) 145 #define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn) 146 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn) 147 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn) 148 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn) 149 #define HIF_GET_USB_DEVICE(scn) ((struct HIF_DEVICE_USB *)scn) 150 #define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn) 151 #define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn) 152 153 #ifdef QCA_WIFI_QCN9224 154 #define NUM_CE_AVAILABLE 16 155 #else 156 #define NUM_CE_AVAILABLE 12 157 #endif 158 /* Add 1 here to store default configuration in index 0 */ 159 #define NUM_CE_CONTEXT (NUM_CE_AVAILABLE + 1) 160 161 #define CE_INTERRUPT_IDX(x) x 162 163 #ifdef WLAN_64BIT_DATA_SUPPORT 164 #define RRI_ON_DDR_MEM_SIZE CE_COUNT * sizeof(uint64_t) 165 #else 166 #define RRI_ON_DDR_MEM_SIZE CE_COUNT * sizeof(uint32_t) 167 #endif 168 169 struct ce_int_assignment { 170 uint8_t msi_idx[NUM_CE_AVAILABLE]; 171 }; 172 173 struct hif_ce_stats { 174 int hif_pipe_no_resrc_count; 175 int ce_ring_delta_fail_count; 176 }; 177 178 #ifdef HIF_DETECTION_LATENCY_ENABLE 179 /** 180 * struct hif_tasklet_running_info - running info of tasklet 181 * @sched_cpuid: id of cpu on which the tasklet was scheduled 182 * @sched_time: time when the tasklet was scheduled 183 * @exec_time: time when the tasklet was executed 184 */ 185 struct hif_tasklet_running_info { 186 int sched_cpuid; 187 qdf_time_t sched_time; 188 qdf_time_t exec_time; 189 }; 190 191 #define HIF_TASKLET_IN_MONITOR CE_COUNT_MAX 192 193 struct hif_latency_detect { 194 qdf_timer_t timer; 195 uint32_t timeout; 196 bool is_timer_started; 197 bool enable_detection; 198 /* threshold when stall happens */ 199 uint32_t threshold; 200 201 /* 202 * Bitmap to indicate the enablement of latency detection for 203 * the tasklets. bit-X represents for tasklet of WLAN_CE_X, 204 * latency detection is enabled on the corresponding tasklet 205 * when a bit is set. 206 * At the same time, this bitmap also indicates the validity of 207 * elements in array 'tasklet_info', bit-X represents for index-X, 208 * the corresponding element is valid when a bit is set. 209 */ 210 qdf_bitmap(tasklet_bmap, HIF_TASKLET_IN_MONITOR); 211 212 /* 213 * Array to record running info of tasklets, info of tasklet 214 * for WLAN_CE_X is stored at index-X. 215 */ 216 struct hif_tasklet_running_info tasklet_info[HIF_TASKLET_IN_MONITOR]; 217 qdf_time_t credit_request_time; 218 qdf_time_t credit_report_time; 219 }; 220 #endif 221 222 /* 223 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 224 * for defined here 225 */ 226 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 227 228 #define HIF_CE_MAX_LATEST_HIST 2 229 230 struct latest_evt_history { 231 uint64_t irq_entry_ts; 232 uint64_t bh_entry_ts; 233 uint64_t bh_resched_ts; 234 uint64_t bh_exit_ts; 235 uint64_t bh_work_ts; 236 int cpu_id; 237 uint32_t ring_hp; 238 uint32_t ring_tp; 239 }; 240 241 struct ce_desc_hist { 242 qdf_atomic_t history_index[CE_COUNT_MAX]; 243 uint8_t ce_id_hist_map[CE_COUNT_MAX]; 244 bool enable[CE_COUNT_MAX]; 245 bool data_enable[CE_COUNT_MAX]; 246 qdf_mutex_t ce_dbg_datamem_lock[CE_COUNT_MAX]; 247 uint32_t hist_index; 248 uint32_t hist_id; 249 void *hist_ev[CE_COUNT_MAX]; 250 struct latest_evt_history latest_evt[HIF_CE_MAX_LATEST_HIST]; 251 }; 252 253 void hif_record_latest_evt(struct ce_desc_hist *ce_hist, 254 uint8_t type, 255 int ce_id, uint64_t time, 256 uint32_t hp, uint32_t tp); 257 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 258 259 /** 260 * struct hif_cfg() - store ini config parameters in hif layer 261 * @ce_status_ring_timer_threshold: ce status ring timer threshold 262 * @ce_status_ring_batch_count_threshold: ce status ring batch count threshold 263 * @disable_wake_irq: disable wake irq 264 */ 265 struct hif_cfg { 266 uint16_t ce_status_ring_timer_threshold; 267 uint8_t ce_status_ring_batch_count_threshold; 268 bool disable_wake_irq; 269 }; 270 271 #ifdef DP_UMAC_HW_RESET_SUPPORT 272 /** 273 * struct hif_umac_reset_ctx - UMAC HW reset context at HIF layer 274 * @intr_tq: Tasklet structure 275 * @irq_handler: IRQ handler 276 * @cb_handler: Callback handler 277 * @cb_ctx: Argument to be passed to @cb_handler 278 * @os_irq: Interrupt number for this IRQ 279 * @irq_configured: Whether the IRQ has been configured 280 */ 281 struct hif_umac_reset_ctx { 282 struct tasklet_struct intr_tq; 283 bool (*irq_handler)(void *cb_ctx); 284 int (*cb_handler)(void *cb_ctx); 285 void *cb_ctx; 286 uint32_t os_irq; 287 bool irq_configured; 288 }; 289 #endif 290 291 #define MAX_SHADOW_REGS 40 292 293 struct hif_softc { 294 struct hif_opaque_softc osc; 295 struct hif_config_info hif_config; 296 struct hif_target_info target_info; 297 void __iomem *mem; 298 void __iomem *mem_ce; 299 void __iomem *mem_cmem; 300 void __iomem *mem_pmm_base; 301 enum qdf_bus_type bus_type; 302 struct hif_bus_ops bus_ops; 303 void *ce_id_to_state[CE_COUNT_MAX]; 304 qdf_device_t qdf_dev; 305 bool hif_init_done; 306 bool request_irq_done; 307 bool ext_grp_irq_configured; 308 bool free_irq_done; 309 uint8_t ce_latency_stats; 310 /* Packet statistics */ 311 struct hif_ce_stats pkt_stats; 312 enum hif_target_status target_status; 313 uint64_t event_enable_mask; 314 315 struct targetdef_s *targetdef; 316 struct ce_reg_def *target_ce_def; 317 struct hostdef_s *hostdef; 318 struct host_shadow_regs_s *host_shadow_regs; 319 320 bool recovery; 321 bool notice_send; 322 bool per_ce_irq; 323 uint32_t ce_irq_summary; 324 /* No of copy engines supported */ 325 unsigned int ce_count; 326 struct ce_int_assignment *int_assignment; 327 atomic_t active_tasklet_cnt; 328 atomic_t active_grp_tasklet_cnt; 329 atomic_t link_suspended; 330 void *vaddr_rri_on_ddr; 331 atomic_t active_wake_req_cnt; 332 qdf_dma_addr_t paddr_rri_on_ddr; 333 #ifdef CONFIG_BYPASS_QMI 334 uint32_t *vaddr_qmi_bypass; 335 qdf_dma_addr_t paddr_qmi_bypass; 336 #endif 337 int linkstate_vote; 338 bool fastpath_mode_on; 339 atomic_t tasklet_from_intr; 340 int htc_htt_tx_endpoint; 341 qdf_dma_addr_t mem_pa; 342 bool athdiag_procfs_inited; 343 #ifdef FEATURE_NAPI 344 struct qca_napi_data napi_data; 345 #endif /* FEATURE_NAPI */ 346 /* stores ce_service_max_yield_time in ns */ 347 unsigned long long ce_service_max_yield_time; 348 uint8_t ce_service_max_rx_ind_flush; 349 struct hif_driver_state_callbacks callbacks; 350 uint32_t hif_con_param; 351 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 352 uint32_t nss_wifi_ol_mode; 353 #endif 354 void *hal_soc; 355 struct hif_ut_suspend_context ut_suspend_ctx; 356 uint32_t hif_attribute; 357 int wake_irq; 358 hif_pm_wake_irq_type wake_irq_type; 359 void (*initial_wakeup_cb)(void *); 360 void *initial_wakeup_priv; 361 #ifdef REMOVE_PKT_LOG 362 /* Handle to pktlog device */ 363 void *pktlog_dev; 364 #endif 365 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 366 /* Pointer to the srng event history */ 367 struct hif_event_history *evt_hist[HIF_NUM_INT_CONTEXTS]; 368 #endif 369 370 /* 371 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 372 * for defined here 373 */ 374 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 375 struct ce_desc_hist hif_ce_desc_hist; 376 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF)*/ 377 #ifdef IPA_OFFLOAD 378 qdf_shared_mem_t *ipa_ce_ring; 379 #endif 380 #ifdef IPA_OPT_WIFI_DP 381 qdf_atomic_t opt_wifi_dp_rtpm_cnt; 382 #endif 383 struct hif_cfg ini_cfg; 384 #ifdef HIF_CE_LOG_INFO 385 qdf_notif_block hif_recovery_notifier; 386 #endif 387 #ifdef HIF_CPU_PERF_AFFINE_MASK 388 /* The CPU hotplug event registration handle */ 389 struct qdf_cpuhp_handler *cpuhp_event_handle; 390 #endif 391 uint32_t irq_unlazy_disable; 392 /* Should the unlzay support for interrupt delivery be disabled */ 393 /* Flag to indicate whether bus is suspended */ 394 bool bus_suspended; 395 bool pktlog_init; 396 #ifdef FEATURE_RUNTIME_PM 397 /* Variable to track the link state change in RTPM */ 398 qdf_atomic_t pm_link_state; 399 #endif 400 #ifdef HIF_DETECTION_LATENCY_ENABLE 401 struct hif_latency_detect latency_detect; 402 #endif 403 #ifdef FEATURE_RUNTIME_PM 404 qdf_runtime_lock_t prevent_linkdown_lock; 405 #endif 406 #ifdef SYSTEM_PM_CHECK 407 qdf_atomic_t sys_pm_state; 408 #endif 409 #if defined(HIF_IPCI) && defined(FEATURE_HAL_DELAYED_REG_WRITE) 410 qdf_atomic_t dp_ep_vote_access; 411 qdf_atomic_t ep_vote_access; 412 #endif 413 /* CMEM address target reserved for host usage */ 414 uint64_t cmem_start; 415 /* CMEM size target reserved */ 416 uint64_t cmem_size; 417 #ifdef DP_UMAC_HW_RESET_SUPPORT 418 struct hif_umac_reset_ctx umac_reset_ctx; 419 #endif 420 #ifdef CONFIG_SHADOW_V3 421 struct pld_shadow_reg_v3_cfg shadow_regs[MAX_SHADOW_REGS]; 422 int num_shadow_registers_configured; 423 #endif 424 #ifdef WLAN_FEATURE_AFFINITY_MGR 425 /* CPU Affinity info of IRQs */ 426 bool affinity_mgr_supported; 427 uint64_t time_threshold; 428 struct hif_cpu_affinity ce_irq_cpu_mask[CE_COUNT_MAX]; 429 struct hif_cpu_affinity irq_cpu_mask[HIF_MAX_GROUP][HIF_MAX_GRP_IRQ]; 430 qdf_cpu_mask allowed_mask; 431 #endif 432 #ifdef FEATURE_DIRECT_LINK 433 struct qdf_mem_multi_page_t dl_recv_pages; 434 int dl_recv_pipe_num; 435 #endif 436 }; 437 438 #if defined(NUM_SOC_PERF_CLUSTER) && (NUM_SOC_PERF_CLUSTER > 1) 439 static inline uint16_t hif_get_perf_cluster_bitmap(void) 440 { 441 return (BIT(CPU_CLUSTER_TYPE_PERF) | BIT(CPU_CLUSTER_TYPE_PERF2)); 442 } 443 #else /* NUM_SOC_PERF_CLUSTER > 1 */ 444 static inline uint16_t hif_get_perf_cluster_bitmap(void) 445 { 446 return BIT(CPU_CLUSTER_TYPE_PERF); 447 } 448 #endif /* NUM_SOC_PERF_CLUSTER > 1 */ 449 450 static inline 451 void *hif_get_hal_handle(struct hif_opaque_softc *hif_hdl) 452 { 453 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 454 455 if (!sc) 456 return NULL; 457 458 return sc->hal_soc; 459 } 460 461 /** 462 * hif_get_cmem_info() - get CMEM address and size from HIF handle 463 * @hif_hdl: HIF handle pointer 464 * @cmem_start: pointer for CMEM address 465 * @cmem_size: pointer for CMEM size 466 * 467 * Return: None. 468 */ 469 static inline 470 void hif_get_cmem_info(struct hif_opaque_softc *hif_hdl, 471 uint64_t *cmem_start, 472 uint64_t *cmem_size) 473 { 474 struct hif_softc *sc = (struct hif_softc *)hif_hdl; 475 476 *cmem_start = sc->cmem_start; 477 *cmem_size = sc->cmem_size; 478 } 479 480 /** 481 * hif_get_num_active_tasklets() - get the number of active 482 * tasklets pending to be completed. 483 * @scn: HIF context 484 * 485 * Returns: the number of tasklets which are active 486 */ 487 static inline int hif_get_num_active_tasklets(struct hif_softc *scn) 488 { 489 return qdf_atomic_read(&scn->active_tasklet_cnt); 490 } 491 492 /* 493 * Max waiting time during Runtime PM suspend to finish all 494 * the tasks. This is in the multiple of 10ms. 495 */ 496 #ifdef PANIC_ON_BUG 497 #define HIF_TASK_DRAIN_WAIT_CNT 200 498 #else 499 #define HIF_TASK_DRAIN_WAIT_CNT 25 500 #endif 501 502 /** 503 * hif_try_complete_tasks() - Try to complete all the pending tasks 504 * @scn: HIF context 505 * 506 * Try to complete all the pending datapath tasks, i.e. tasklets, 507 * DP group tasklets and works which are queued, in a given time 508 * slot. 509 * 510 * Returns: QDF_STATUS_SUCCESS if all the tasks were completed 511 * QDF error code, if the time slot exhausted 512 */ 513 QDF_STATUS hif_try_complete_tasks(struct hif_softc *scn); 514 515 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 516 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 517 { 518 return !!(sc->nss_wifi_ol_mode); 519 } 520 #else 521 static inline bool hif_is_nss_wifi_enabled(struct hif_softc *sc) 522 { 523 return false; 524 } 525 #endif 526 527 static inline uint8_t hif_is_attribute_set(struct hif_softc *sc, 528 uint32_t hif_attrib) 529 { 530 return sc->hif_attribute == hif_attrib; 531 } 532 533 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 534 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 535 { 536 struct hif_softc *scn = (struct hif_softc *)hif_handle; 537 538 scn->event_enable_mask = HIF_EVENT_HIST_ENABLE_MASK; 539 } 540 #else 541 static inline void hif_set_event_hist_mask(struct hif_opaque_softc *hif_handle) 542 { 543 } 544 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 545 546 A_target_id_t hif_get_target_id(struct hif_softc *scn); 547 void hif_dump_pipe_debug_count(struct hif_softc *scn); 548 void hif_display_bus_stats(struct hif_opaque_softc *scn); 549 void hif_clear_bus_stats(struct hif_opaque_softc *scn); 550 bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count); 551 void hif_shutdown_device(struct hif_opaque_softc *hif_ctx); 552 int hif_bus_configure(struct hif_softc *scn); 553 void hif_cancel_deferred_target_sleep(struct hif_softc *scn); 554 int hif_config_ce(struct hif_softc *scn); 555 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_ctx); 556 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num); 557 void hif_unconfig_ce(struct hif_softc *scn); 558 void hif_ce_prepare_config(struct hif_softc *scn); 559 QDF_STATUS hif_ce_open(struct hif_softc *scn); 560 void hif_ce_close(struct hif_softc *scn); 561 int athdiag_procfs_init(void *scn); 562 void athdiag_procfs_remove(void); 563 /* routine to modify the initial buffer count to be allocated on an os 564 * platform basis. Platform owner will need to modify this as needed 565 */ 566 qdf_size_t init_buffer_count(qdf_size_t maxSize); 567 568 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg); 569 int hif_get_device_type(uint32_t device_id, 570 uint32_t revision_id, 571 uint32_t *hif_type, uint32_t *target_type); 572 /*These functions are exposed to HDD*/ 573 void hif_nointrs(struct hif_softc *scn); 574 void hif_bus_close(struct hif_softc *ol_sc); 575 QDF_STATUS hif_bus_open(struct hif_softc *ol_sc, 576 enum qdf_bus_type bus_type); 577 QDF_STATUS hif_enable_bus(struct hif_softc *ol_sc, struct device *dev, 578 void *bdev, const struct hif_bus_id *bid, enum hif_enable_type type); 579 void hif_disable_bus(struct hif_softc *scn); 580 void hif_bus_prevent_linkdown(struct hif_softc *scn, bool flag); 581 int hif_bus_get_context_size(enum qdf_bus_type bus_type); 582 void hif_read_phy_mem_base(struct hif_softc *scn, qdf_dma_addr_t *bar_value); 583 uint32_t hif_get_conparam(struct hif_softc *scn); 584 struct hif_driver_state_callbacks *hif_get_callbacks_handle( 585 struct hif_softc *scn); 586 bool hif_is_driver_unloading(struct hif_softc *scn); 587 bool hif_is_load_or_unload_in_progress(struct hif_softc *scn); 588 bool hif_is_recovery_in_progress(struct hif_softc *scn); 589 bool hif_is_target_ready(struct hif_softc *scn); 590 591 /** 592 * hif_get_bandwidth_level() - API to get the current bandwidth level 593 * @hif_handle: HIF Context 594 * 595 * Return: PLD bandwidth level 596 */ 597 int hif_get_bandwidth_level(struct hif_opaque_softc *hif_handle); 598 599 void hif_wlan_disable(struct hif_softc *scn); 600 int hif_target_sleep_state_adjust(struct hif_softc *scn, 601 bool sleep_ok, 602 bool wait_for_it); 603 604 #ifdef DP_MEM_PRE_ALLOC 605 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 606 qdf_size_t size, 607 qdf_dma_addr_t *paddr, 608 uint32_t ring_type, 609 uint8_t *is_mem_prealloc); 610 611 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 612 qdf_size_t size, 613 void *vaddr, 614 qdf_dma_addr_t paddr, 615 qdf_dma_context_t memctx, 616 uint8_t is_mem_prealloc); 617 618 /** 619 * hif_prealloc_get_multi_pages() - gets pre-alloc DP multi-pages memory 620 * @scn: HIF context 621 * @desc_type: descriptor type 622 * @elem_size: single element size 623 * @elem_num: total number of elements should be allocated 624 * @pages: multi page information storage 625 * @cacheable: coherent memory or cacheable memory 626 * 627 * Return: None 628 */ 629 void hif_prealloc_get_multi_pages(struct hif_softc *scn, uint32_t desc_type, 630 qdf_size_t elem_size, uint16_t elem_num, 631 struct qdf_mem_multi_page_t *pages, 632 bool cacheable); 633 634 /** 635 * hif_prealloc_put_multi_pages() - puts back pre-alloc DP multi-pages memory 636 * @scn: HIF context 637 * @desc_type: descriptor type 638 * @pages: multi page information storage 639 * @cacheable: coherent memory or cacheable memory 640 * 641 * Return: None 642 */ 643 void hif_prealloc_put_multi_pages(struct hif_softc *scn, uint32_t desc_type, 644 struct qdf_mem_multi_page_t *pages, 645 bool cacheable); 646 #else 647 static inline 648 void *hif_mem_alloc_consistent_unaligned(struct hif_softc *scn, 649 qdf_size_t size, 650 qdf_dma_addr_t *paddr, 651 uint32_t ring_type, 652 uint8_t *is_mem_prealloc) 653 { 654 return qdf_mem_alloc_consistent(scn->qdf_dev, 655 scn->qdf_dev->dev, 656 size, 657 paddr); 658 } 659 660 static inline 661 void hif_mem_free_consistent_unaligned(struct hif_softc *scn, 662 qdf_size_t size, 663 void *vaddr, 664 qdf_dma_addr_t paddr, 665 qdf_dma_context_t memctx, 666 uint8_t is_mem_prealloc) 667 { 668 return qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 669 size, vaddr, paddr, memctx); 670 } 671 672 static inline 673 void hif_prealloc_get_multi_pages(struct hif_softc *scn, uint32_t desc_type, 674 qdf_size_t elem_size, uint16_t elem_num, 675 struct qdf_mem_multi_page_t *pages, 676 bool cacheable) 677 { 678 qdf_mem_multi_pages_alloc(scn->qdf_dev, pages, 679 elem_size, elem_num, 0, cacheable); 680 } 681 682 static inline 683 void hif_prealloc_put_multi_pages(struct hif_softc *scn, uint32_t desc_type, 684 struct qdf_mem_multi_page_t *pages, 685 bool cacheable) 686 { 687 qdf_mem_multi_pages_free(scn->qdf_dev, pages, 0, 688 cacheable); 689 } 690 #endif 691 692 /** 693 * hif_get_rx_ctx_id() - Returns NAPI instance ID based on CE ID 694 * @ctx_id: Rx CE context ID 695 * @hif_hdl: HIF Context 696 * 697 * Return: Rx instance ID 698 */ 699 int hif_get_rx_ctx_id(int ctx_id, struct hif_opaque_softc *hif_hdl); 700 void hif_ramdump_handler(struct hif_opaque_softc *scn); 701 #ifdef HIF_USB 702 void hif_usb_get_hw_info(struct hif_softc *scn); 703 void hif_usb_ramdump_handler(struct hif_opaque_softc *scn); 704 #else 705 static inline void hif_usb_get_hw_info(struct hif_softc *scn) {} 706 static inline void hif_usb_ramdump_handler(struct hif_opaque_softc *scn) {} 707 #endif 708 709 /** 710 * hif_wake_interrupt_handler() - interrupt handler for standalone wake irq 711 * @irq: the irq number that fired 712 * @context: the opaque pointer passed to request_irq() 713 * 714 * Return: an irq return type 715 */ 716 irqreturn_t hif_wake_interrupt_handler(int irq, void *context); 717 718 #if defined(HIF_SNOC) 719 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc); 720 #elif defined(HIF_IPCI) 721 static inline bool 722 hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 723 { 724 return !(hif_sc->recovery); 725 } 726 #else 727 static inline 728 bool hif_is_target_register_access_allowed(struct hif_softc *hif_sc) 729 { 730 return true; 731 } 732 #endif 733 734 #ifdef ADRASTEA_RRI_ON_DDR 735 void hif_uninit_rri_on_ddr(struct hif_softc *scn); 736 #else 737 static inline 738 void hif_uninit_rri_on_ddr(struct hif_softc *scn) {} 739 #endif 740 void hif_cleanup_static_buf_to_target(struct hif_softc *scn); 741 742 #ifdef FEATURE_RUNTIME_PM 743 /** 744 * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occurring 745 * @scn: hif context 746 * @is_get: prevent linkdown if true otherwise allow 747 * 748 * this api should only be called as part of bus prevent linkdown 749 */ 750 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get); 751 #else 752 static inline 753 void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get) 754 { 755 } 756 #endif 757 758 #ifdef HIF_HAL_REG_ACCESS_SUPPORT 759 void hif_reg_window_write(struct hif_softc *scn, 760 uint32_t offset, uint32_t value); 761 uint32_t hif_reg_window_read(struct hif_softc *scn, uint32_t offset); 762 #endif 763 764 #endif /* __HIF_MAIN_H__ */ 765