/linux-6.12.1/drivers/gpu/drm/i915/gvt/ |
D | display.c | 70 if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled() 86 if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled() 188 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change() 194 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= in emulate_monitor_status_change() 196 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change() 197 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change() 198 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change() 199 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change() 203 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &= in emulate_monitor_status_change() 207 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= in emulate_monitor_status_change() [all …]
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D | mmio.c | 255 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; in intel_vgpu_reset_mmio() 258 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; in intel_vgpu_reset_mmio() 261 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in intel_vgpu_reset_mmio() 264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio() 266 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio() 268 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio() 270 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio() 272 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio() 274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio() 276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio() [all …]
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D | fb_decoder.c | 158 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask; in intel_vgpu_get_stride() 220 val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)); in intel_vgpu_decode_primary_plane() 254 plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane() 270 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane() 273 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & in intel_vgpu_decode_primary_plane() 277 val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe)); in intel_vgpu_decode_primary_plane() 351 val = vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)); in intel_vgpu_decode_cursor_plane() 377 plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane() 388 val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe)); in intel_vgpu_decode_cursor_plane() 394 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane() [all …]
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D | vgpu.c | 44 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; in populate_pvinfo_page() 45 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; in populate_pvinfo_page() 46 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; in populate_pvinfo_page() 47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page() 49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; in populate_pvinfo_page() 50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; in populate_pvinfo_page() 51 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; in populate_pvinfo_page() 53 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = in populate_pvinfo_page() 55 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = in populate_pvinfo_page() 57 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = in populate_pvinfo_page() [all …]
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D | edid.c | 131 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller() 133 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller() 165 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus0_mmio_write() 166 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; in gmbus0_mmio_write() 172 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; in gmbus0_mmio_write() 174 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in gmbus0_mmio_write() 201 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; in gmbus1_mmio_write() 202 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; in gmbus1_mmio_write() 250 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus1_mmio_write() 262 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; in gmbus1_mmio_write() [all …]
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D | mmio_context.c | 237 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit() 267 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit() 294 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit() 400 vgpu_vreg_t(vgpu, reg) = 0; in handle_tlb_pending_event() 434 old_v = vgpu_vreg_t(pre, offset); in switch_mocs() 438 new_v = vgpu_vreg_t(next, offset); in switch_mocs() 452 old_v = vgpu_vreg_t(pre, l3_offset); in switch_mocs() 456 new_v = vgpu_vreg_t(next, l3_offset); in switch_mocs() 507 vgpu_vreg_t(pre, mmio->reg) = in switch_mmio() 510 vgpu_vreg_t(pre, mmio->reg) &= in switch_mmio() [all …]
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D | handlers.c | 352 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write() 384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write() 385 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; in pch_pp_control_mmio_write() 386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; in pch_pp_control_mmio_write() 387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; in pch_pp_control_mmio_write() 390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write() 469 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); in bdw_vgpu_get_dp_bitrate() 483 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate() 495 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate() 507 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); in bdw_vgpu_get_dp_bitrate() [all …]
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D | cmd_parser.c | 1400 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); in gen8_check_mi_display_flip() 1401 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip() 1404 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & in gen8_check_mi_display_flip() 1406 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip() 1425 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), in gen8_update_plane_mmio_from_mi_display_flip() 1428 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), in gen8_update_plane_mmio_from_mi_display_flip() 1430 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip() 1433 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), in gen8_update_plane_mmio_from_mi_display_flip() 1435 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip() 1440 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++; in gen8_update_plane_mmio_from_mi_display_flip()
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D | scheduler.c | 652 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx() 971 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; in update_guest_context() 972 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; in update_guest_context()
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D | gvt.h | 457 #define vgpu_vreg_t(vgpu, reg) \ macro
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D | gtt.c | 1057 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & in vgpu_ips_enabled()
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