Lines Matching refs:vgpu_vreg_t
352 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write()
384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
385 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; in pch_pp_control_mmio_write()
386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; in pch_pp_control_mmio_write()
387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; in pch_pp_control_mmio_write()
390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write()
469 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); in bdw_vgpu_get_dp_bitrate()
483 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate()
495 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()
507 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); in bdw_vgpu_get_dp_bitrate()
509 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); in bdw_vgpu_get_dp_bitrate()
533 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); in bdw_vgpu_get_dp_bitrate()
569 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); in bxt_vgpu_get_dp_bitrate()
578 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; in bxt_vgpu_get_dp_bitrate()
579 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) in bxt_vgpu_get_dp_bitrate()
581 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); in bxt_vgpu_get_dp_bitrate()
583 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); in bxt_vgpu_get_dp_bitrate()
585 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); in bxt_vgpu_get_dp_bitrate()
587 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); in bxt_vgpu_get_dp_bitrate()
611 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && in skl_vgpu_get_dp_bitrate()
612 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { in skl_vgpu_get_dp_bitrate()
613 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & in skl_vgpu_get_dp_bitrate()
623 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & in skl_vgpu_get_dp_bitrate()
660 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) & in vgpu_update_refresh_rate()
676 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)); in vgpu_update_refresh_rate()
677 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)); in vgpu_update_refresh_rate()
680 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); in vgpu_update_refresh_rate()
681 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); in vgpu_update_refresh_rate()
809 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) in ddi_buf_ctl_mmio_write()
827 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
829 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
870 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) in check_fdi_rx_train_status()
873 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) in check_fdi_rx_train_status()
875 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) in check_fdi_rx_train_status()
933 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; in update_fdi_rx_iir_status()
939 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; in update_fdi_rx_iir_status()
943 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= in update_fdi_rx_iir_status()
964 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); in dp_tp_ctl_mmio_write()
1023 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); in pri_surf_mmio_write()
1025 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; in pri_surf_mmio_write()
1027 if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
1045 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in spr_surf_mmio_write()
1047 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) in spr_surf_mmio_write()
1066 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1067 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; in reg50080_mmio_write()
1069 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1400 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> in sbi_data_mmio_read()
1402 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & in sbi_data_mmio_read()
1427 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> in sbi_ctl_mmio_write()
1429 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & in sbi_ctl_mmio_write()
1433 vgpu_vreg_t(vgpu, SBI_DATA)); in sbi_ctl_mmio_write()
1687 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); in mailbox_write()
1883 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write()
1885 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write()
1890 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in bxt_gt_disp_pwron_write()
1892 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in bxt_gt_disp_pwron_write()