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Searched refs:rtw_write32_mask (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Drtw8822c.c380 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); in rtw8822c_dac_bb_setting()
381 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); in rtw8822c_dac_bb_setting()
382 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); in rtw8822c_dac_bb_setting()
384 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
385 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
390 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); in rtw8822c_dac_bb_setting()
391 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); in rtw8822c_dac_bb_setting()
419 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); in rtw8822c_dac_cal_adc()
524 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); in rtw8822c_dac_cal_step2()
525 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); in rtw8822c_dac_cal_step2()
[all …]
Drtw8822b.c89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); in rtw8822b_phy_set_param()
172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
479 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); in rtw8822b_set_channel_cca()
[all …]
Drtw8821c.c189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in rtw8821c_phy_set_param()
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA); in rtw8821c_switch_rf_set()
290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA); in rtw8821c_switch_rf_set()
295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA); in rtw8821c_switch_rf_set()
296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA); in rtw8821c_switch_rf_set()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
[all …]
Drtw8723d.c105 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_phy_set_param()
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_phy_set_param()
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); in rtw8723d_phy_set_param()
301 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); in rtw8723d_cfg_notch()
302 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
307 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
313 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); in rtw8723d_cfg_notch()
314 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
319 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
322 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); in rtw8723d_cfg_notch()
[all …]
Drtw8703b.c669 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8703b_phy_set_param()
729 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8703b_phy_set_param()
730 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); in rtw8703b_phy_set_param()
757 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); in rtw8703b_cfg_notch()
758 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8703b_cfg_notch()
763 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8703b_cfg_notch()
771 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); in rtw8703b_cfg_notch()
772 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8703b_cfg_notch()
777 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8703b_cfg_notch()
780 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); in rtw8703b_cfg_notch()
[all …]
Drtw8723x.c350 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); in rtw8723x_set_tx_power_index_by_rate()
386 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); in __rtw8723x_false_alarm_statistics()
387 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); in __rtw8723x_false_alarm_statistics()
388 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); in __rtw8723x_false_alarm_statistics()
389 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); in __rtw8723x_false_alarm_statistics()
427 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); in __rtw8723x_false_alarm_statistics()
428 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); in __rtw8723x_false_alarm_statistics()
429 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); in __rtw8723x_false_alarm_statistics()
430 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); in __rtw8723x_false_alarm_statistics()
431 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); in __rtw8723x_false_alarm_statistics()
[all …]
Defuse.c16 rtw_write32_mask(rtwdev, REG_LDO_EFUSE_CTRL, BIT_MASK_EFUSE_BANK_SEL, in switch_efuse_bank()
130 rtw_write32_mask(rtwdev, REG_EFUSE_CTRL, 0x3ff00, addr); in rtw_read8_physical_efuse()
Drtw8822b.h112 rtw_write32_mask(rtwdev, addr, mask, data); in _rtw_write32s_mask()
113 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
Drtw8821c.h110 rtw_write32_mask(rtwdev, addr, mask, data); in _rtw_write32s_mask()
111 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
Dphy.c128 rtw_write32_mask(rtwdev, in rtw_phy_set_edcca_th()
132 rtw_write32_mask(rtwdev, in rtw_phy_set_edcca_th()
236 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); in rtw_phy_dig_write()
242 rtw_write32_mask(rtwdev, addr, mask, igi); in rtw_phy_dig_write()
1023 rtw_write32_mask(rtwdev, direct_addr, mask, data); in rtw_phy_write_rf_reg()
1751 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); in rtw_load_rfk_table()
1752 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); in rtw_load_rfk_table()
1753 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); in rtw_load_rfk_table()
1754 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); in rtw_load_rfk_table()
1755 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); in rtw_load_rfk_table()
Dmac80211.c357 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_TXOP_LMT, params->txop); in __rtw_conf_tx()
358 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMAX, ecw_max); in __rtw_conf_tx()
359 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMIN, ecw_min); in __rtw_conf_tx()
360 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_AIFS, aifs); in __rtw_conf_tx()
Drtw8723x.h466 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723x_iqk_config_path_ctrl()
498 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, in rtw8723x_iqk_config_lte_path_gnt()
Dhci.h234 rtw_write32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) in rtw_write32_mask() function
Dbf.c376 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE, in rtw_bf_phy_init()
Dmain.c929 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); in rtw_vif_port_config()
934 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); in rtw_vif_port_config()
2329 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); in rtw_swap_reg_mask()
2330 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); in rtw_swap_reg_mask()
Dpci.c1295 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); in rtw_mdio_write()
1443 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, in rtw_pci_interface_cfg()
1506 rtw_write32_mask(rtwdev, REG_ANAPARSW_MAC_0, BIT_CF_L_V2, 0x1); in rtw_pci_phy_cfg()