669 	rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,  in rtw8703b_phy_set_param()
729 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8703b_phy_set_param()
730 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);  in rtw8703b_phy_set_param()
757 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);  in rtw8703b_cfg_notch()
758 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
763 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
771 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);  in rtw8703b_cfg_notch()
772 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
777 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
780 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);  in rtw8703b_cfg_notch()
781 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
786 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
789 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);  in rtw8703b_cfg_notch()
790 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
795 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
798 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);  in rtw8703b_cfg_notch()
799 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
804 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
807 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);  in rtw8703b_cfg_notch()
808 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
813 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
819 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
820 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
911 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
912 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
913 		rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE,  in rtw8703b_set_channel_bb()
919 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
920 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
923 		rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,  in rtw8703b_set_channel_bb()
925 		rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,  in rtw8703b_set_channel_bb()
928 		rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26),  in rtw8703b_set_channel_bb()
1109 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);  in rtw8703b_iqk_one_shot()
1139 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8703b_iqk_txrx_path_post()
1222 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_tx_path()
1249 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8703b_iqk_rx_path()
1276 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1310 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1343 	rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);  in rtw8703b_iqk_one_round()
1389 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);  in rtw8703b_iqk_one_round()
1410 	rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,  in rtw8703b_iqk_fill_a_matrix()
1412 	rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,  in rtw8703b_iqk_fill_a_matrix()
1417 	rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8703b_iqk_fill_a_matrix()
1419 	rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,  in rtw8703b_iqk_fill_a_matrix()
1421 	rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,  in rtw8703b_iqk_fill_a_matrix()
1436 	rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,  in rtw8703b_iqk_fill_a_matrix()
1578 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8703b_set_iqk_matrix_by_result()
1591 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,  in rtw8703b_set_iqk_matrix_by_result()
1621 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,  in rtw8703b_set_iqk_matrix()
1631 		rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS,  in rtw8703b_set_iqk_matrix()