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/linux-6.12.1/arch/powerpc/platforms/powermac/
Dcache.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level cache management functions
5 * (In fact the only thing that is Apple-specific is that we assume
15 #include <asm/feature-fixups.h>
45 sync
52 sync
58 sync
60 sync
62 /* Disp-flush L1. We have a weird problem here that I never
64 * results in a non-working flush. We use that workaround for
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/linux-6.12.1/tools/testing/selftests/powerpc/ptrace/
Dchild.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Helper functions to sync execution between parent and child processes.
29 #define CHILD_FAIL_IF(x, sync) \ argument
34 (sync)->child_gave_up = true; \
35 prod_parent(sync); \
36 return 1; \
40 #define PARENT_FAIL_IF(x, sync) \ argument
45 (sync)->parent_gave_up = true; \
46 prod_child(sync); \
47 return 1; \
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/linux-6.12.1/drivers/gpu/drm/i915/selftests/
Di915_syncmap.c41 for (d = 0; d < depth - 1; d++) { in __sync_print()
42 if (last & BIT(depth - d - 1)) in __sync_print()
47 *sz -= len; in __sync_print()
49 len = scnprintf(buf, *sz, "%x-> ", idx); in __sync_print()
51 *sz -= len; in __sync_print()
55 len = scnprintf(buf, *sz, "0x%016llx", p->prefix << p->height << SHIFT); in __sync_print()
57 *sz -= len; in __sync_print()
58 X = (p->height + SHIFT) / 4; in __sync_print()
59 scnprintf(buf - X, *sz + X, "%*s", X, "XXXXXXXXXXXXXXXXX"); in __sync_print()
61 if (!p->height) { in __sync_print()
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/linux-6.12.1/arch/parisc/kernel/
Dperf_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
46 sync ; follow ERS
100 ;* %r24 - original DR2 value
101 ;* %r1 - scratch
102 ;* %r29 - scratch
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
121 depdi,z 1,DR2_SLOW_RET,1,%r29
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/linux-6.12.1/arch/powerpc/kernel/
Dl2cr_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
16 - Terry: Updated for workaround to HID0[DPM] processor bug
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
29 Please e-mail updates to this file to me, thanks!
36 #include <asm/feature-fixups.h>
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Dcpu_setup_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
100 bne 1f /* don't invalidate the D-cache */
102 1: sync
104 sync
106 sync
118 sync
120 sync /* on 604e/604r */
122 sync
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Dmisc_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains miscellaneous low-level functions.
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
21 #include <asm/asm-offsets.h>
27 #include <asm/feature-fixups.h>
47 sync
53 sync
58 sync
62 sync
68 sync
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Dcpu_setup_ppc970.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-offsets.h>
28 sync
31 sync
34 sync
37 sync
41 li r3,0x1200 /* enable i-fetch cacheability */
50 sync
104 sync
109 clrldi r0,r0,1 /* clear LPES0 */
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/linux-6.12.1/tools/testing/selftests/kvm/
Dmemslot_perf_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * A memslot-related performance benchmark.
36 #define MEM_TEST_SIZE (MEM_SIZE - MEM_EXTRA_SIZE)
45 #define MEM_TEST_MAP_SIZE (MEM_SIZE_MAP - MEM_EXTRA_SIZE)
68 * architecture slots memory-per-slot memory-on-last-slot
69 * --------------------------------------------------------------
70 * x86-4KB 32763 16KB 160KB
71 * arm64-4KB 32766 16KB 112KB
72 * arm64-16KB 32766 16KB 112KB
73 * arm64-64KB 8192 64KB 128KB
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/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_sync.c1 // SPDX-License-Identifier: MIT
8 #include <linux/dma-fence-array.h>
38 mmdrop(ufence->mm); in user_fence_destroy()
44 kref_get(&ufence->refcount); in user_fence_get()
49 kref_put(&ufence->refcount, user_fence_destroy); in user_fence_put()
60 return ERR_PTR(-EFAULT); in user_fence_create()
64 return ERR_PTR(-ENOMEM); in user_fence_create()
66 ufence->xe = xe; in user_fence_create()
67 kref_init(&ufence->refcount); in user_fence_create()
68 ufence->addr = ptr; in user_fence_create()
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/linux-6.12.1/arch/powerpc/platforms/52xx/
Dmpc52xx_sleep.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
16 sync; isync;
21 lwz r8, 0x14(r6) /* intr->main_mask */
25 sync
29 stw r8, 0x40(r6) /* intr->main_emulate */
30 sync
33 1:
34 cmpi cr0, r10, 1
35 bne cr0, 1b
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Dlite5200_sleep.S1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define SC_MODE_EN (1<<31)
12 #define SC_CKE (1<<30)
13 #define SC_REF_EN (1<<28)
14 #define SC_SOFT_PRE (1<<1)
21 #define CDM_SDRAM (1<<3)
32 sync; \
41 /* ---------------------------------------------------------------------- */
42 /* low-power mode with help of M68HLC908QT1 */
50 /* setup wakeup address for u-boot at physical location 0x0 */
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/linux-6.12.1/drivers/usb/serial/
Dipaq.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2001 - 2002
37 { USB_DEVICE(0x0104, 0x00BE) }, /* Socket USB Sync */
38 { USB_DEVICE(0x03F0, 0x1016) }, /* HP USB Sync */
39 { USB_DEVICE(0x03F0, 0x1116) }, /* HP USB Sync 1611 */
40 { USB_DEVICE(0x03F0, 0x1216) }, /* HP USB Sync 1612 */
41 { USB_DEVICE(0x03F0, 0x2016) }, /* HP USB Sync 1620 */
42 { USB_DEVICE(0x03F0, 0x2116) }, /* HP USB Sync 1621 */
43 { USB_DEVICE(0x03F0, 0x2216) }, /* HP USB Sync 1622 */
44 { USB_DEVICE(0x03F0, 0x3016) }, /* HP USB Sync 1630 */
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/linux-6.12.1/arch/sparc/kernel/
Dcherrs.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 membar #Sync
12 membar #Sync
16 .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
21 membar #Sync
25 membar #Sync
28 mov 1, %g1
29 .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
34 membar #Sync
38 membar #Sync
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dqcom,q6dsp-lpass-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - qcom,q6afe-dais
20 '#sound-dai-cells':
21 const: 1
23 '#address-cells':
24 const: 1
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/linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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/linux-6.12.1/arch/mips/include/asm/
Dsync.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
7 * II-A of the MIPS Architecture Reference Manual, which can be found here:
9 * https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06
13 * 1) Completion barriers, which ensure that a memory operation has actually
27 * actually need to complete - they just need to get far enough that all
43 * No sync instruction at all; used to allow code to nullify the effect of the
46 #define __SYNC_none -1
49 * A full completion barrier; all memory accesses appearing prior to this sync
51 * appearing after this sync instruction in program order.
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/linux-6.12.1/arch/mips/alchemy/common/
Dsleeper.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 sw $1, PT_R1(sp)
74 sync
76 sync
93 la t0, 1f
101 1: lui a0, 0xb400 /* mem_xxx */
103 sync
105 sync
107 sync
119 la t0, 1f
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/linux-6.12.1/drivers/gpu/drm/sti/
Dsti_vtg.c1 // SPDX-License-Identifier: GPL-2.0
64 #define VTG_IRQ_TOP BIT(1)
74 #define AWG_DELAY_HD (-9)
75 #define AWG_DELAY_ED (-8)
76 #define AWG_DELAY_SD (-7)
156 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset()
168 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); in vtg_set_output_window()
169 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); in vtg_set_output_window()
185 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, in vtg_set_hsync_vsync_pos() argument
193 clocksperline = mode->htotal; in vtg_set_hsync_vsync_pos()
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/linux-6.12.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
15 # Sync Width 3.813 us 0.064 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
40 # Sync Width 2.032 us 0.080 ms
43 # 2 chars 1 lines
52 mode "640x480-75"
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
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/linux-6.12.1/drivers/video/fbdev/
Dcontrolfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 /* Vertical parameters are in units of 1/2 scan line */
47 struct preg vesync; /* vert end sync */
48 struct preg vssync; /* vert start sync */
52 struct preg hperiod; /* horiz period - 2 */
55 struct preg hesync; /* horiz end sync */
56 struct preg hssync; /* horiz start sync */
57 struct preg heq; /* half horiz sync len */
59 struct preg hserr; /* horiz period - horiz sync len */
74 /* Vertical parameters are in units of 1/2 scan line */
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/linux-6.12.1/drivers/net/ethernet/xscale/
Dixp46x_ts.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 u32 control; /* 0x00 Time Sync Control Register */
27 u32 event; /* 0x04 Time Sync Event Register */
28 u32 addend; /* 0x08 Time Sync Addend Register */
29 u32 accum; /* 0x0C Time Sync Accumulator Register */
30 u32 test; /* 0x10 Time Sync Test Register */
46 /* 0x00 Time Sync Control Register Bits */
47 #define TSCR_AMM (1<<3)
48 #define TSCR_ASM (1<<2)
49 #define TSCR_TTM (1<<1)
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/linux-6.12.1/net/caif/
Dcfserl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2010
25 spinlock_t sync; member
45 this->layer.receive = cfserl_receive; in cfserl_create()
46 this->layer.transmit = cfserl_transmit; in cfserl_create()
47 this->layer.ctrlcmd = cfserl_ctrlcmd; in cfserl_create()
48 this->usestx = use_stx; in cfserl_create()
49 spin_lock_init(&this->sync); in cfserl_create()
50 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); in cfserl_create()
51 return &this->layer; in cfserl_create()
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/linux-6.12.1/arch/powerpc/boot/
Dio.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Low-level I/O routines.
16 __asm__ __volatile__("lbz%U1%X1 %0,%1; twi 0,%0,0; isync" in in_8()
23 __asm__ __volatile__("stb%U0%X0 %1,%0; sync" in out_8()
31 __asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync" in in_le16()
41 __asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync" in in_be16()
48 __asm__ __volatile__("sthbrx %1,0,%2; sync" : "=m" (*addr) in out_le16()
54 __asm__ __volatile__("sth%U0%X0 %1,%0; sync" in out_be16()
62 __asm__ __volatile__("lwbrx %0,0,%1; twi 0,%0,0; isync" in in_le32()
71 __asm__ __volatile__("lwz%U1%X1 %0,%1; twi 0,%0,0; isync" in in_be32()
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