Lines Matching +full:sync +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
22 - fsl,mpc866-tsa
23 - const: fsl,cpm1-tsa
27 - description: SI (Serial Interface) register base
28 - description: SI RAM base
30 reg-names:
32 - const: si_regs
33 - const: si_ram
35 '#address-cells':
36 const: 1
38 '#size-cells':
42 '^tdm@[0-1]$':
52 maximum: 1
54 The TDM number for this TDM, 0 for TDMa and 1 for TDMb
56 fsl,common-rxtx-pins:
59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
61 Without the 'fsl,common-rxtx-pins' property, the four pins are used.
62 With the 'fsl,common-rxtx-pins' property, two pins are used.
67 - description: External clock connected to L1RSYNC pin
68 - description: External clock connected to L1RCLK pin
69 - description: External clock connected to L1TSYNC pin
70 - description: External clock connected to L1TCLK pin
72 clock-names:
75 - const: l1rsync
76 - const: l1rclk
77 - const: l1tsync
78 - const: l1tclk
80 fsl,rx-frame-sync-delay-bits:
81 enum: [0, 1, 2, 3]
84 Receive frame sync delay in number of bits.
85 Indicates the delay between the Rx sync and the first bit of the Rx
86 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
88 fsl,tx-frame-sync-delay-bits:
89 enum: [0, 1, 2, 3]
92 Transmit frame sync delay in number of bits.
93 Indicates the delay between the Tx sync and the first bit of the Tx
94 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
96 fsl,clock-falling-edge:
100 edge). If 'clock-falling-edge' is not present, data is sent on the
103 fsl,fsync-rising-edge:
106 Frame sync pulses are sampled with the rising edge of the channel
107 clock. If 'fsync-rising-edge' is not present, pulses are sampled with
110 fsl,double-speed-clock:
116 '^fsl,[rt]x-ts-routes$':
117 $ref: /schemas/types.yaml#/definitions/uint32-matrix
119 A list of tuple that indicates the Tx or Rx time-slots routes.
122 - description:
123 The number of time-slots
124 minimum: 1
126 - description: |
128 (dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
129 - 0: No destination
130 - 1: SCC2
131 - 2: SCC3
132 - 3: SCC4
133 - 4: SMC1
134 - 5: SMC2
135 enum: [0, 1, 2, 3, 4, 5]
136 minItems: 1
140 # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
142 - if:
144 - fsl,common-rxtx-pins
149 clock-names:
155 clock-names:
159 - reg
160 - clocks
161 - clock-names
164 - compatible
165 - reg
166 - reg-names
167 - '#address-cells'
168 - '#size-cells'
173 - |
174 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
177 compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
180 reg-names = "si_regs", "si_ram";
182 #address-cells = <1>;
183 #size-cells = <0>;
190 clock-names = "l1rsync", "l1rclk";
192 fsl,common-rxtx-pins;
193 fsl,fsync-rising-edge;
195 fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
197 <1 0>, /* TS 26 */
200 fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
202 <1 0>, /* TS 26 */