platforms/powermac/cache.S

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * This file contains low-level cache management functions
5  * (In fact the only thing that is Apple-specific is that we assume
15 #include <asm/feature-fixups.h>
45 	sync
52 	sync
58 	sync
60 	sync
62 	/* Disp-flush L1. We have a weird problem here that I never
64 	 * results in a non-working flush. We use that workaround for
65 	 * now until I finally understand what's going on. --BenH
73 	bne+	1f
76 1:	li	r4,0x4000
78 1:	lwz	r0,0(r4)
80 	bdnz	1b
81 	sync
88 	sync
91 	sync
96 	sync
100 	/* Set to data-only (pre-745x bit) */
105 1:	mtspr	SPRN_L2CR,r3
106 3:	sync
108 	b	1f
110 3:	sync
112 	b	1b
113 1:	/* disp-flush L2. The interesting thing here is that the L2 can be
115 	 * but that is probbaly fine. We disp-flush over 4Mb to be safe
120 1:	lwz	r0,0(r4)
122 	bdnz	1b
123 	sync
128 1:	dcbf	0,r4
130 	bdnz	1b
131 	sync
139 1:	mtspr	SPRN_L2CR,r5
140 3:	sync
142 	b	1f
144 3:	sync
146 	b	1b
147 1:	sync
149 	/* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
152 	sync
156 1:	mfspr	r3,SPRN_L2CR
158 	bne	1b
162 	sync
164 	sync
170 	sync
174 	sync
178 	sync
181 	sync
195 	sync
201 	sync
207 	sync
229 1:
232         bdnz    1b
239         sync
240 1:
243         bdnz    1b
250 1:	mtctr	r5
253 	sync
258 	rlwinm	r4,r4,1,24,30	/* move on to the next way */
259 	ori	r4,r4,1
261 	bne	1b
265 	sync
267 	sync
278 1:	mtspr	SPRN_L2CR,r0	/* lock the L2 cache */
279 3:	sync
281 	b	1f
283 3:	sync
285 	b	1b
286 1:	sync
289 	sync
294 	sync
299 1:	mtspr	SPRN_L2CR,r3	/* disable the L2 cache */
300 3:	sync
302 	b	1f
304 3:	sync
306 	b	1b
307 1:	sync
311 	sync
313 1:	mfspr	r4,SPRN_L2CR
315 	bne	1b
316 	sync
325 	sync
327 	sync
330 	sync
336 	sync
338 	sync
341 1:	mfspr	r4,SPRN_L3CR
343 	bne	1b
344 	sync
350 	sync