Searched +full:quadspi +full:- +full:memory (Results 1 – 16 of 16) sorted by relevance
/linux-6.12.1/Documentation/devicetree/bindings/spi/ |
D | fsl,spi-fsl-qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale Quad Serial Peripheral Interface (QuadSPI) 10 - Han Xu <han.xu@nxp.com> 13 - $ref: spi-controller.yaml# 18 - enum: 19 - fsl,vf610-qspi 20 - fsl,imx6sx-qspi [all …]
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D | atmel,quadspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/spi/atmel,quadspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tudor Ambarus <tudor.ambarus@linaro.org> 13 - $ref: spi-controller.yaml# 18 - atmel,sama5d2-qspi 19 - microchip,sam9x60-qspi 20 - microchip,sama7g5-qspi 21 - microchip,sama7g5-ospi [all …]
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/linux-6.12.1/drivers/spi/ |
D | spi-fsl-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Freescale QuadSPI driver. 18 * Based on the original fsl-quadspi.c SPI NOR driver: 42 #include <linux/spi/spi-mem.h> 158 #define LUT_PAD(x) (fls(x) - 1) 164 * --------------------------------------------------- 166 * --------------------------------------------------- 188 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) 279 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian() 284 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock() [all …]
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D | atmel-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0 11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. 25 #include <linux/spi/spi-mem.h> 69 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) 228 u32 value = readl_relaxed(aq->regs + offset); in atmel_qspi_read() 233 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, in atmel_qspi_read() 245 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value, in atmel_qspi_write() 249 writel_relaxed(value, aq->regs + offset); in atmel_qspi_write() 255 if (op->cmd.buswidth != mode->cmd_buswidth) in atmel_qspi_is_compatible() 258 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) in atmel_qspi_is_compatible() [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/vf/ |
D | vfxxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 #include "vf610-pinfunc.h" 6 #include <dt-bindings/clock/vf610-clock.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/gpio/gpio.h> 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <24000000>; 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1012a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1012A family SoC. 6 * Copyright 2019-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 23 rtic-a = &rtic_a; [all …]
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D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 37 #address-cells = <1>; [all …]
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D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 5 * Copyright 2017-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 26 #address-cells = <1>; [all …]
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D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 6 * Copyright 2017-2020 NXP 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 32 #address-cells = <1>; [all …]
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D | imx8mq.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 7 #include <dt-bindings/clock/imx8mq-clock.h> 8 #include <dt-bindings/power/imx8mq-power.h> 9 #include <dt-bindings/reset/imx8mq-reset.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include "dt-bindings/input/input.h" 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interconnect/imx8mq.h> [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
D | imx6sx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 #include <dt-bindings/clock/imx6sx-clock.h> 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include "imx6sx-pinfunc.h" 12 #address-cells = <1>; 13 #size-cells = <1>; 16 * pre-existing /chosen node to be available to insert the 60 #address-cells = <1>; [all …]
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D | imx6ul.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 #include <dt-bindings/clock/imx6ul-clock.h> 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include "imx6ul-pinfunc.h" 12 #address-cells = <1>; 13 #size-cells = <1>; 16 * pre-existing /chosen node to be available to insert the 57 #address-cells = <1>; [all …]
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D | imx7s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 6 #include <dt-bindings/clock/imx7d-clock.h> 7 #include <dt-bindings/power/imx7-power.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/reset/imx7-reset.h> 12 #include "imx7d-pinfunc.h" 15 #address-cells = <1>; 16 #size-cells = <1>; [all …]
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/linux-6.12.1/drivers/mtd/spi-nor/controllers/ |
D | nxp-spifi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 * Based on Freescale QuadSPI driver: 18 #include <linux/mtd/spi-nor.h> 68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd() 71 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd() 81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset() 82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset() 85 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset() 94 if (!spifi->memory_mode) in nxp_spifi_set_memory_mode_off() 99 dev_err(spifi->dev, "unable to enter command mode\n"); in nxp_spifi_set_memory_mode_off() [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/ls/ |
D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/thermal/thermal.h> 10 #address-cells = <2>; 11 #size-cells = <2>; 12 interrupt-parent = <&gic>; 30 #address-cells = <1>; 31 #size-cells = <0>; 34 compatible = "arm,cortex-a7"; [all …]
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