1 // SPDX-License-Identifier: GPL-2.0-only
7  * Based on Freescale QuadSPI driver:
18 #include <linux/mtd/spi-nor.h>
68 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,  in nxp_spifi_wait_for_cmd()
71 		dev_warn(spifi->dev, "command timed out\n");  in nxp_spifi_wait_for_cmd()
81 	writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);  in nxp_spifi_reset()
82 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,  in nxp_spifi_reset()
85 		dev_warn(spifi->dev, "state reset timed out\n");  in nxp_spifi_reset()
94 	if (!spifi->memory_mode)  in nxp_spifi_set_memory_mode_off()
99 		dev_err(spifi->dev, "unable to enter command mode\n");  in nxp_spifi_set_memory_mode_off()
101 		spifi->memory_mode = false;  in nxp_spifi_set_memory_mode_off()
111 	if (spifi->memory_mode)  in nxp_spifi_set_memory_mode_on()
114 	writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);  in nxp_spifi_set_memory_mode_on()
115 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,  in nxp_spifi_set_memory_mode_on()
118 		dev_err(spifi->dev, "unable to enter memory mode\n");  in nxp_spifi_set_memory_mode_on()
120 		spifi->memory_mode = true;  in nxp_spifi_set_memory_mode_on()
128 	struct nxp_spifi *spifi = nor->priv;  in nxp_spifi_read_reg()
140 	writel(cmd, spifi->io_base + SPIFI_CMD);  in nxp_spifi_read_reg()
142 	while (len--)  in nxp_spifi_read_reg()
143 		*buf++ = readb(spifi->io_base + SPIFI_DATA);  in nxp_spifi_read_reg()
151 	struct nxp_spifi *spifi = nor->priv;  in nxp_spifi_write_reg()
164 	writel(cmd, spifi->io_base + SPIFI_CMD);  in nxp_spifi_write_reg()
166 	while (len--)  in nxp_spifi_write_reg()
167 		writeb(*buf++, spifi->io_base + SPIFI_DATA);  in nxp_spifi_write_reg()
175 	struct nxp_spifi *spifi = nor->priv;  in nxp_spifi_read()
182 	memcpy_fromio(buf, spifi->flash_base + from, len);  in nxp_spifi_read()
190 	struct nxp_spifi *spifi = nor->priv;  in nxp_spifi_write()
199 	writel(to, spifi->io_base + SPIFI_ADDR);  in nxp_spifi_write()
204 	      SPIFI_CMD_OPCODE(nor->program_opcode) |  in nxp_spifi_write()
205 	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);  in nxp_spifi_write()
206 	writel(cmd, spifi->io_base + SPIFI_CMD);  in nxp_spifi_write()
209 		writeb(buf[i], spifi->io_base + SPIFI_DATA);  in nxp_spifi_write()
220 	struct nxp_spifi *spifi = nor->priv;  in nxp_spifi_erase()
228 	writel(offs, spifi->io_base + SPIFI_ADDR);  in nxp_spifi_erase()
231 	      SPIFI_CMD_OPCODE(nor->erase_opcode) |  in nxp_spifi_erase()
232 	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);  in nxp_spifi_erase()
233 	writel(cmd, spifi->io_base + SPIFI_CMD);  in nxp_spifi_erase()
240 	switch (spifi->nor.read_proto) {  in nxp_spifi_setup_memory_cmd()
242 		spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;  in nxp_spifi_setup_memory_cmd()
246 		spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;  in nxp_spifi_setup_memory_cmd()
249 		dev_err(spifi->dev, "unsupported SPI read mode\n");  in nxp_spifi_setup_memory_cmd()
250 		return -EINVAL;  in nxp_spifi_setup_memory_cmd()
253 	/* Memory mode supports address length between 1 and 4 */  in nxp_spifi_setup_memory_cmd()
254 	if (spifi->nor.addr_nbytes < 1 || spifi->nor.addr_nbytes > 4)  in nxp_spifi_setup_memory_cmd()
255 		return -EINVAL;  in nxp_spifi_setup_memory_cmd()
257 	spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |  in nxp_spifi_setup_memory_cmd()
258 		       SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |  in nxp_spifi_setup_memory_cmd()
259 		       SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);  in nxp_spifi_setup_memory_cmd()
267 	nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,  in nxp_spifi_dummy_id_read()
291 	if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {  in nxp_spifi_setup_flash()
302 			dev_err(spifi->dev, "unsupported rx-bus-width\n");  in nxp_spifi_setup_flash()
303 			return -EINVAL;  in nxp_spifi_setup_flash()
307 	if (of_property_read_bool(np, "spi-cpha"))  in nxp_spifi_setup_flash()
310 	if (of_property_read_bool(np, "spi-cpol"))  in nxp_spifi_setup_flash()
336 		dev_err(spifi->dev, "only mode 0 and 3 supported\n");  in nxp_spifi_setup_flash()
337 		return -EINVAL;  in nxp_spifi_setup_flash()
340 	writel(ctrl, spifi->io_base + SPIFI_CTRL);  in nxp_spifi_setup_flash()
342 	spifi->nor.dev   = spifi->dev;  in nxp_spifi_setup_flash()
343 	spi_nor_set_flash_node(&spifi->nor, np);  in nxp_spifi_setup_flash()
344 	spifi->nor.priv  = spifi;  in nxp_spifi_setup_flash()
345 	spifi->nor.controller_ops = &nxp_spifi_controller_ops;  in nxp_spifi_setup_flash()
356 	nxp_spifi_dummy_id_read(&spifi->nor);  in nxp_spifi_setup_flash()
358 	ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);  in nxp_spifi_setup_flash()
360 		dev_err(spifi->dev, "device scan failed\n");  in nxp_spifi_setup_flash()
366 		dev_err(spifi->dev, "memory command setup failed\n");  in nxp_spifi_setup_flash()
370 	ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);  in nxp_spifi_setup_flash()
372 		dev_err(spifi->dev, "mtd device parse failed\n");  in nxp_spifi_setup_flash()
385 	spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);  in nxp_spifi_probe()
387 		return -ENOMEM;  in nxp_spifi_probe()
389 	spifi->io_base = devm_platform_ioremap_resource_byname(pdev, "spifi");  in nxp_spifi_probe()
390 	if (IS_ERR(spifi->io_base))  in nxp_spifi_probe()
391 		return PTR_ERR(spifi->io_base);  in nxp_spifi_probe()
393 	spifi->flash_base = devm_platform_ioremap_resource_byname(pdev, "flash");  in nxp_spifi_probe()
394 	if (IS_ERR(spifi->flash_base))  in nxp_spifi_probe()
395 		return PTR_ERR(spifi->flash_base);  in nxp_spifi_probe()
397 	spifi->clk_spifi = devm_clk_get_enabled(&pdev->dev, "spifi");  in nxp_spifi_probe()
398 	if (IS_ERR(spifi->clk_spifi)) {  in nxp_spifi_probe()
399 		dev_err(&pdev->dev, "spifi clock not found or unable to enable\n");  in nxp_spifi_probe()
400 		return PTR_ERR(spifi->clk_spifi);  in nxp_spifi_probe()
403 	spifi->clk_reg = devm_clk_get_enabled(&pdev->dev, "reg");  in nxp_spifi_probe()
404 	if (IS_ERR(spifi->clk_reg)) {  in nxp_spifi_probe()
405 		dev_err(&pdev->dev, "reg clock not found or unable to enable\n");  in nxp_spifi_probe()
406 		return PTR_ERR(spifi->clk_reg);  in nxp_spifi_probe()
409 	spifi->dev = &pdev->dev;  in nxp_spifi_probe()
414 	writel(0, spifi->io_base + SPIFI_IDATA);  in nxp_spifi_probe()
415 	writel(0, spifi->io_base + SPIFI_MCMD);  in nxp_spifi_probe()
418 	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);  in nxp_spifi_probe()
420 		dev_err(&pdev->dev, "no SPI flash device to configure\n");  in nxp_spifi_probe()
421 		return -ENODEV;  in nxp_spifi_probe()
427 		dev_err(&pdev->dev, "unable to setup flash chip\n");  in nxp_spifi_probe()
438 	mtd_device_unregister(&spifi->nor.mtd);  in nxp_spifi_remove()
442 	{.compatible = "nxp,lpc1773-spifi"},
451 		.name = "nxp-spifi",