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/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/linux-6.12.1/drivers/net/dsa/mv88e6xxx/
Dglobal2.h16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
28 /* Offset 0x01: Interrupt Mask Register */
[all …]
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am62a7.dtsi17 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0x8000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
69 reg = <0x002>;
72 i-cache-size = <0x8000>;
[all …]
Dk3-am62p5.dtsi16 #size-cells = <0>;
38 cpu0: cpu@0 {
40 reg = <0x000>;
43 i-cache-size = <0x8000>;
46 d-cache-size = <0x8000>;
50 clocks = <&k3_clks 135 0>;
55 reg = <0x001>;
58 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
65 clocks = <&k3_clks 136 0>;
[all …]
Dk3-am654.dtsi13 #size-cells = <0>;
36 cpu0: cpu@0 {
38 reg = <0x000>;
41 i-cache-size = <0x8000>;
44 d-cache-size = <0x8000>;
52 reg = <0x001>;
55 i-cache-size = <0x8000>;
58 d-cache-size = <0x8000>;
66 reg = <0x100>;
69 i-cache-size = <0x8000>;
[all …]
Dk3-am625.dtsi17 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0x8000>;
47 d-cache-size = <0x8000>;
52 clocks = <&k3_clks 135 0>;
58 reg = <0x001>;
61 i-cache-size = <0x8000>;
64 d-cache-size = <0x8000>;
69 clocks = <&k3_clks 136 0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x000>;
52 i-cache-size = <0x8000>;
55 d-cache-size = <0x8000>;
63 reg = <0x0 0x100>;
65 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
76 reg = <0x0 0x200>;
[all …]
Djuno.dts37 #size-cells = <0>;
68 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 arm,psci-suspend-param = <0x1010000>;
87 A57_0: cpu@0 {
89 reg = <0x0 0x0>;
92 i-cache-size = <0xc000>;
95 d-cache-size = <0x8000>;
99 clocks = <&scpi_dvfs 0>;
[all …]
Djuno-r2.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A72_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
Djuno-r1.dts38 #size-cells = <0>;
69 CPU_SLEEP_0: cpu-sleep-0 {
71 arm,psci-suspend-param = <0x0010000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
80 arm,psci-suspend-param = <0x1010000>;
88 A57_0: cpu@0 {
90 reg = <0x0 0x0>;
93 i-cache-size = <0xc000>;
96 d-cache-size = <0x8000>;
100 clocks = <&scpi_dvfs 0>;
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0x0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0xc000>;
40 reg = <0x1>;
42 d-cache-size = <0x8000>;
45 i-cache-size = <0xc000>;
54 reg = <0x2>;
56 d-cache-size = <0x8000>;
[all …]
/linux-6.12.1/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dpci-msi.txt13 * Bits [2:0] are the Function number.
67 reg = <0xa 0x1>;
74 reg = <0xf 0x1>;
82 msi-map = <0x0 &msi_a 0x0 0x10000>,
95 reg = <0xa 0x1>;
102 reg = <0xf 0x1>;
110 msi-map = <0x0 &msi_a 0x0 0x100>,
111 msi-map-mask = <0xff>
124 reg = <0xa 0x1>;
131 reg = <0xf 0x1>;
[all …]
Dpci-iommu.txt13 * Bits [2:0] are the Function number.
56 reg = <0xa 0x1>;
62 reg = <0xf 0x1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
83 reg = <0xa 0x1>;
89 reg = <0xf 0x1>;
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
98 iommu-map-mask = <0xfff8>;
111 reg = <0xa 0x1>;
117 reg = <0xf 0x1>;
[all …]
/linux-6.12.1/include/linux/mfd/wm831x/
Dpmu.h14 * R16387 (0x4003) - Power State
16 #define WM831X_CHIP_ON 0x8000 /* CHIP_ON */
17 #define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */
20 #define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */
21 #define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */
24 #define WM831X_REF_LP 0x1000 /* REF_LP */
25 #define WM831X_REF_LP_MASK 0x1000 /* REF_LP */
28 #define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */
31 #define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */
32 #define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm2837.dtsi8 ranges = <0x7e000000 0x3f000000 0x1000000>,
9 <0x40000000 0x40000000 0x00001000>;
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 reg = <0x40000000 0x100>;
30 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
39 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
54 cpu-release-addr = <0x0 0x000000d8>;
55 d-cache-size = <0x8000>;
[all …]
Dbcm2836.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
51 v7_cpu0: cpu@0 {
54 reg = <0xf00>;
56 d-cache-size = <0x8000>;
59 i-cache-size = <0x8000>;
[all …]
/linux-6.12.1/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dtracepoints.rst36 …tc-6546 [010] ...1 2679.704889: mlx5e_stats_flower: cookie=0000000060eb3d6a bytes=0 packets=0 la…
59 …: mlx5_esw_bridge_fdb_entry_init: net_device=enp8s0f0_0 addr=e4:fd:05:08:00:02 vid=0 flags=0 used=0
66 …x5_esw_bridge_fdb_entry_cleanup: net_device=enp8s0f0_1 addr=e4:fd:05:08:00:03 vid=0 flags=0 used=16
74 …lx5_esw_bridge_fdb_entry_refresh: net_device=enp8s0f0_0 addr=e4:fd:05:08:00:02 vid=3 flags=0 used=0
115 … mlx5_esw_vport_qos_create: (0000:82:00.0) vport=2 tsar_ix=4 bw_share=0, max_rate=0 group=00000000…
159 …..... 24610.188722: mlx5_sf_add: (0000:06:00.0) port_index=32768 controller=0 hw_id=0x8000 sfnum=88
166 … [038] ..... 26300.404749: mlx5_sf_free: (0000:06:00.0) port_index=32768 controller=0 hw_id=0x8000
173 …08] ..... 3669.635095: mlx5_sf_activate: (0000:08:00.0) port_index=32768 controller=0 hw_id=0x8000
180 …] ..... 4015.969467: mlx5_sf_deactivate: (0000:08:00.0) port_index=32768 controller=0 hw_id=0x8000
187 …5 [031] ..... 26296.385259: mlx5_sf_hwc_alloc: (0000:06:00.0) controller=0 hw_id=0x8000 sfnum=88
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amd/
Damd-seattle-cpus.dtsi5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
43 CPU0: cpu@0 {
46 reg = <0x0>;
49 i-cache-size = <0xC000>;
52 d-cache-size = <0x8000>;
62 reg = <0x1>;
65 i-cache-size = <0xC000>;
68 d-cache-size = <0x8000>;
77 reg = <0x100>;
[all …]
/linux-6.12.1/drivers/pcmcia/
Dtcic.h33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux-6.12.1/drivers/mfd/
Dwm97xx-core.c23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
[all …]
/linux-6.12.1/include/linux/mfd/
Dwm8400-private.h16 #define WM8400_REGISTER_COUNT 0x55
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
[all …]

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