Searched refs:SOC_RESET_CONTROL_CE_RST_MASK (Results 1 – 9 of 9) sorted by relevance
93 #define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET macro291 .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK,
162 #define SOC_RESET_CONTROL_CE_RST_MASK \ macro
164 #define SOC_RESET_CONTROL_CE_RST_MASK \ macro
77 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK macro
78 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK macro
81 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK macro
101 #define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000 macro102 #define SOC_RESET_CONTROL_CE_RST_GET(x) (((x) & SOC_RESET_CONTROL_CE_RST_MASK) >> SOC_RESE…103 …TROL_CE_RST_SET(x) (((x) << SOC_RESET_CONTROL_CE_RST_LSB) & SOC_RESET_CONTROL_CE_RST_MASK)
449 #define SOC_RESET_CONTROL_CE_RST_MASK \ macro
676 val |= SOC_RESET_CONTROL_CE_RST_MASK; in hif_pci_device_warm_reset()687 val &= ~SOC_RESET_CONTROL_CE_RST_MASK; in hif_pci_device_warm_reset()