1 /* 2 * Copyright (c) 2015,2016,2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "qdf_module.h" 20 21 #if defined(QCA9984_HEADERS_DEF) 22 #define QCA9984 1 23 24 #define WLAN_HEADERS 1 25 #include "common_drv.h" 26 #include "QCA9984/soc_addrs.h" 27 #include "QCA9984/extra/hw/apb_map.h" 28 #include "QCA9984/hw/gpio_athr_wlan_reg.h" 29 #ifdef WLAN_HEADERS 30 31 #include "QCA9984/extra/hw/wifi_top_reg_map.h" 32 #include "QCA9984/hw/rtc_soc_reg.h" 33 34 #endif 35 #include "QCA9984/hw/si_reg.h" 36 #include "QCA9984/extra/hw/pcie_local_reg.h" 37 #include "QCA9984/hw/ce_wrapper_reg_csr.h" 38 39 #include "QCA9984/extra/hw/soc_core_reg.h" 40 #include "QCA9984/hw/soc_pcie_reg.h" 41 #include "QCA9984/extra/hw/ce_reg_csr.h" 42 #include <QCA9984/hw/interface/rx_location_info.h> 43 #include <QCA9984/hw/interface/rx_pkt_end.h> 44 #include <QCA9984/hw/interface/rx_phy_ppdu_end.h> 45 #include <QCA9984/hw/interface/rx_timing_offset.h> 46 #include <QCA9984/hw/interface/rx_location_info.h> 47 #include <QCA9984/hw/tlv/rx_ppdu_start.h> 48 #include <QCA9984/hw/tlv/rx_ppdu_end.h> 49 #include <QCA9984/hw/tlv/rx_mpdu_start.h> 50 #include <QCA9984/hw/tlv/rx_mpdu_end.h> 51 #include <QCA9984/hw/tlv/rx_msdu_start.h> 52 #include <QCA9984/hw/tlv/rx_msdu_end.h> 53 #include <QCA9984/hw/tlv/rx_attention.h> 54 #include <QCA9984/hw/tlv/rx_frag_info.h> 55 #include <QCA9984/hw/datastruct/msdu_link_ext.h> 56 #include <QCA9984/hw/emu_phy_reg.h> 57 58 /* Base address is defined in pcie_local_reg.h. Macros which access the 59 * registers include the base address in their definition. 60 */ 61 #define PCIE_LOCAL_BASE_ADDRESS 0 62 63 #define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) 64 #define DRAM_BASE_ADDRESS TARG_DRAM_START 65 66 /* Backwards compatibility -- TBDXXX */ 67 68 #define MISSING 0 69 70 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB 71 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK 72 #define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK 73 #define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK 74 #define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS 75 #define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS 76 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS 77 #define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS 78 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK 79 #define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS 80 #define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS 81 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 82 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 83 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 84 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 85 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 86 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 87 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 88 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 89 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 90 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 91 #define LOCAL_SCRATCH_OFFSET 0x18 92 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 93 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 94 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 95 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 96 #define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS 97 #define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS 98 #define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS 99 #define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS 100 #define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS 101 #define SI_CS_OFFSET SI_CS_ADDRESS 102 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 103 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 104 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 105 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 106 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 107 #define MBOX_BASE_ADDRESS MISSING 108 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 109 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 110 #define INT_STATUS_ENABLE_CPU_LSB MISSING 111 #define INT_STATUS_ENABLE_CPU_MASK MISSING 112 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 113 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 114 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 115 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 116 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 117 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 118 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 119 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 120 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 121 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 122 #define INT_STATUS_ENABLE_ADDRESS MISSING 123 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 124 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 125 #define HOST_INT_STATUS_ADDRESS MISSING 126 #define CPU_INT_STATUS_ADDRESS MISSING 127 #define ERROR_INT_STATUS_ADDRESS MISSING 128 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 129 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 130 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 131 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 132 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 133 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 134 #define COUNT_DEC_ADDRESS MISSING 135 #define HOST_INT_STATUS_CPU_MASK MISSING 136 #define HOST_INT_STATUS_CPU_LSB MISSING 137 #define HOST_INT_STATUS_ERROR_MASK MISSING 138 #define HOST_INT_STATUS_ERROR_LSB MISSING 139 #define HOST_INT_STATUS_COUNTER_MASK MISSING 140 #define HOST_INT_STATUS_COUNTER_LSB MISSING 141 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 142 #define WINDOW_DATA_ADDRESS MISSING 143 #define WINDOW_READ_ADDR_ADDRESS MISSING 144 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 145 /* MAC Descriptor */ 146 #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) 147 /* GPIO Register */ 148 #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS 149 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 150 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 151 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 152 /* CE descriptor */ 153 #define CE_SRC_DESC_SIZE_DWORD 2 154 #define CE_DEST_DESC_SIZE_DWORD 2 155 #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 156 #define CE_SRC_DESC_INFO_OFFSET_DWORD 1 157 #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 158 #define CE_DEST_DESC_INFO_OFFSET_DWORD 1 159 #if _BYTE_ORDER == _BIG_ENDIAN 160 #define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 161 #define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 162 #define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 163 #define CE_SRC_DESC_INFO_GATHER_SHIFT 15 164 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 165 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 166 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 167 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 168 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 169 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 170 #define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF 171 #define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 172 #else 173 #define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF 174 #define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 175 #define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 176 #define CE_SRC_DESC_INFO_GATHER_SHIFT 16 177 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 178 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 179 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 180 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 181 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 182 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 183 #define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 184 #define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 185 #endif 186 #if _BYTE_ORDER == _BIG_ENDIAN 187 #define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 188 #define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 189 #define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 190 #define CE_DEST_DESC_INFO_GATHER_SHIFT 15 191 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 192 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 193 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 194 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 195 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 196 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 197 #define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF 198 #define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 199 #else 200 #define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF 201 #define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 202 #define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 203 #define CE_DEST_DESC_INFO_GATHER_SHIFT 16 204 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 205 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 206 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 207 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 208 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 209 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 210 #define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 211 #define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 212 #endif 213 214 #define MY_TARGET_DEF QCA9984_TARGETdef 215 #define MY_HOST_DEF QCA9984_HOSTdef 216 #define MY_CEREG_DEF QCA9984_CE_TARGETdef 217 #define MY_TARGET_BOARD_DATA_SZ QCA9984_BOARD_DATA_SZ 218 #define MY_TARGET_BOARD_EXT_DATA_SZ QCA9984_BOARD_EXT_DATA_SZ 219 #include "targetdef.h" 220 #include "hostdef.h" 221 qdf_export_symbol(QCA9984_CE_TARGETdef); 222 #else 223 #include "common_drv.h" 224 #include "targetdef.h" 225 #include "hostdef.h" 226 struct targetdef_s *QCA9984_TARGETdef; 227 struct hostdef_s *QCA9984_HOSTdef; 228 #endif /* QCA9984_HEADERS_DEF */ 229 qdf_export_symbol(QCA9984_TARGETdef); 230 qdf_export_symbol(QCA9984_HOSTdef); 231 232