1 /* 2 * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REGTABLE_PCIE_H_ 20 #define _REGTABLE_PCIE_H_ 21 22 #define MISSING 0 23 24 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \ 25 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 26 #define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \ 27 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1) 28 #define A_SOC_CORE_SPARE_1_REGISTER \ 29 (scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER) 30 #define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \ 31 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1) 32 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \ 33 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1) 34 #define A_SOC_PCIE_PCIE_SCRATCH_0 \ 35 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0) 36 #define A_SOC_PCIE_PCIE_SCRATCH_1 \ 37 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1) 38 #define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \ 39 (scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA) 40 #define A_SOC_PCIE_PCIE_SCRATCH_2 \ 41 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2) 42 /* end Q6 iHelium emu registers */ 43 44 #define PCIE_INTR_FIRMWARE_ROUTE_MASK \ 45 (scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK) 46 #define A_SOC_CORE_SPARE_0_REGISTER \ 47 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 48 #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 49 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 50 #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 51 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 52 #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 53 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 54 #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 55 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 56 #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 57 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 58 #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 59 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 60 #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 61 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 62 #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 63 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 64 #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 65 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 66 #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 67 #define WLAN_SYSTEM_SLEEP_OFFSET \ 68 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 69 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 70 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 71 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 72 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 73 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 74 #define CLOCK_CONTROL_SI0_CLK_MASK \ 75 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 76 #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 77 #define RESET_CONTROL_MBOX_RST_MASK \ 78 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 79 #define RESET_CONTROL_SI0_RST_MASK \ 80 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 81 #define WLAN_RESET_CONTROL_OFFSET \ 82 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 83 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 84 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 85 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 86 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 87 #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 88 #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 89 #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 90 #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 91 #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 92 #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 93 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 94 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 95 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 96 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 97 #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 98 #define SI_CONFIG_I2C_MASK \ 99 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 100 #define SI_CONFIG_POS_SAMPLE_LSB \ 101 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 102 #define SI_CONFIG_POS_SAMPLE_MASK \ 103 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 104 #define SI_CONFIG_INACTIVE_CLK_LSB \ 105 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 106 #define SI_CONFIG_INACTIVE_CLK_MASK \ 107 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 108 #define SI_CONFIG_INACTIVE_DATA_LSB \ 109 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 110 #define SI_CONFIG_INACTIVE_DATA_MASK \ 111 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 112 #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 113 #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 114 #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 115 #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 116 #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 117 #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 118 #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 119 #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 120 #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 121 #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 122 #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 123 #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 124 #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 125 #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 126 #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 127 #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 128 #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 129 #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 130 #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 131 #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 132 #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 133 #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 134 #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 135 #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 136 #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 137 #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 138 #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 139 #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 140 #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 141 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 142 #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 143 #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 144 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 145 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 146 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 147 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 148 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 149 #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 150 #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 151 #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 152 #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 153 #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 154 #define CE_COUNT (scn->targetdef->d_CE_COUNT) 155 #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 156 #define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 157 #define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 158 #define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 159 #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 160 #define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 161 #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 162 #define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \ 163 A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 164 #define SOC_RESET_CONTROL_CE_RST_MASK \ 165 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 166 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 167 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 168 #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 169 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 170 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 171 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 172 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 173 #define SOC_LF_TIMER_STATUS0_ADDRESS \ 174 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 175 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 176 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 177 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 178 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 179 180 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 181 (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 182 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 183 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 184 (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 185 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 186 187 /* hif_pci.c */ 188 #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 189 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 190 #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 191 #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 192 #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 193 #define CHIP_ID_REVISION_GET(x) \ 194 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 195 #define CHIP_ID_VERSION_GET(x) \ 196 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 197 /* hif_pci.c end */ 198 199 /* misc */ 200 #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 201 #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 202 #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 203 /* end */ 204 205 /* copy_engine.c */ 206 /* end */ 207 /* PLL start */ 208 #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 209 #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 210 #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 211 #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 212 #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 213 #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 214 #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 215 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 216 #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 217 #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 218 #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 219 #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 220 #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 221 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 222 #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 223 #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 224 #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 225 #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 226 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 227 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 228 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 229 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 230 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 231 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 232 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 233 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 234 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 235 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 236 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 237 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 238 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 239 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 240 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 241 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 242 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 243 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 244 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 245 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 246 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 247 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 248 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 249 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 250 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 251 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 252 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 253 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 254 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 255 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 256 #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 257 #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 258 #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 259 #define WLAN_PLL_CONTROL_DIV_RESET \ 260 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 261 #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 262 #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 263 #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 264 #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 265 #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 266 #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 267 #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 268 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 269 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 270 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 271 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 272 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 273 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 274 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 275 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 276 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 277 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 278 #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 279 #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 280 #define SOC_CPU_CLOCK_STANDARD_MSB \ 281 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 282 #define SOC_CPU_CLOCK_STANDARD_LSB \ 283 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 284 #define SOC_CPU_CLOCK_STANDARD_MASK \ 285 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 286 /* PLL end */ 287 288 #define FW_CPU_PLL_CONFIG \ 289 (scn->targetdef->d_FW_CPU_PLL_CONFIG) 290 291 #define WIFICMN_PCIE_BAR_REG_ADDRESS \ 292 (sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS) 293 294 /* htt tx */ 295 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \ 296 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK) 297 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \ 298 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK) 299 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \ 300 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK) 301 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \ 302 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK) 303 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \ 304 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB) 305 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \ 306 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB) 307 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \ 308 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB) 309 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \ 310 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB) 311 312 #define CE_CMD_ADDRESS \ 313 (scn->targetdef->d_CE_CMD_ADDRESS) 314 #define CE_CMD_HALT_MASK \ 315 (scn->targetdef->d_CE_CMD_HALT_MASK) 316 #define CE_CMD_HALT_STATUS_MASK \ 317 (scn->targetdef->d_CE_CMD_HALT_STATUS_MASK) 318 #define CE_CMD_HALT_STATUS_LSB \ 319 (scn->targetdef->d_CE_CMD_HALT_STATUS_LSB) 320 321 #define SI_CONFIG_ERR_INT_MASK \ 322 (scn->targetdef->d_SI_CONFIG_ERR_INT_MASK) 323 #define SI_CONFIG_ERR_INT_LSB \ 324 (scn->targetdef->d_SI_CONFIG_ERR_INT_LSB) 325 #define GPIO_ENABLE_W1TS_LOW_ADDRESS \ 326 (scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS) 327 #define GPIO_PIN0_CONFIG_LSB \ 328 (scn->targetdef->d_GPIO_PIN0_CONFIG_LSB) 329 #define GPIO_PIN0_PAD_PULL_LSB \ 330 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB) 331 #define GPIO_PIN0_PAD_PULL_MASK \ 332 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK) 333 334 #define SOC_CHIP_ID_REVISION_MSB \ 335 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB) 336 337 #define FW_AXI_MSI_ADDR \ 338 (scn->targetdef->d_FW_AXI_MSI_ADDR) 339 #define FW_AXI_MSI_DATA \ 340 (scn->targetdef->d_FW_AXI_MSI_DATA) 341 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \ 342 (scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 343 #define FPGA_VERSION_ADDRESS \ 344 (scn->targetdef->d_FPGA_VERSION_ADDRESS) 345 346 /* SET macros */ 347 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 348 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 349 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 350 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 351 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 352 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 353 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 354 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 355 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 356 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 357 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 358 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 359 #define SI_CONFIG_DIVIDER_SET(x) \ 360 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 361 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 362 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 363 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 364 #define LPO_CAL_ENABLE_SET(x) \ 365 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 366 #define CPU_CLOCK_STANDARD_SET(x) \ 367 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 368 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 369 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 370 /* copy_engine.c */ 371 /* end */ 372 /* PLL start */ 373 #define EFUSE_XTAL_SEL_GET(x) \ 374 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 375 #define EFUSE_XTAL_SEL_SET(x) \ 376 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 377 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 378 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 379 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 380 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 381 #define BB_PLL_CONFIG_FRAC_GET(x) \ 382 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 383 #define BB_PLL_CONFIG_FRAC_SET(x) \ 384 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 385 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 386 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 387 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 388 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 389 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 390 (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 391 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 392 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 393 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 394 (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 395 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 396 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 397 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 398 (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 399 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 400 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 401 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 402 (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 403 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 404 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 405 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 406 (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 407 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 408 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 409 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 410 (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 411 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 412 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 413 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 414 (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 415 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 416 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 417 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 418 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 419 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 420 (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 421 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 422 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 423 /* PLL end */ 424 #define WLAN_GPIO_PIN0_CONFIG_SET(x) \ 425 (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) 426 #define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \ 427 (((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK) 428 #define SI_CONFIG_ERR_INT_SET(x) \ 429 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) 430 431 432 #ifdef QCA_WIFI_3_0_ADRASTEA 433 #define Q6_ENABLE_REGISTER_0 \ 434 (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 435 #define Q6_ENABLE_REGISTER_1 \ 436 (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 437 #define Q6_CAUSE_REGISTER_0 \ 438 (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 439 #define Q6_CAUSE_REGISTER_1 \ 440 (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 441 #define Q6_CLEAR_REGISTER_0 \ 442 (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 443 #define Q6_CLEAR_REGISTER_1 \ 444 (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 445 #endif 446 447 #ifdef CONFIG_BYPASS_QMI 448 #define BYPASS_QMI_TEMP_REGISTER \ 449 (scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER) 450 #endif 451 452 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START) 453 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 454 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 455 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 456 #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT) 457 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 458 #define INT_STATUS_ENABLE_ERROR_LSB \ 459 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 460 #define INT_STATUS_ENABLE_ERROR_MASK \ 461 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 462 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 463 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 464 #define INT_STATUS_ENABLE_COUNTER_LSB \ 465 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 466 #define INT_STATUS_ENABLE_COUNTER_MASK \ 467 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 468 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 469 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 470 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 471 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 472 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 473 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 474 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 475 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 476 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 477 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 478 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 479 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 480 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 481 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 482 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 483 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 484 #define INT_STATUS_ENABLE_ADDRESS \ 485 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 486 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 487 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 488 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 489 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 490 #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 491 #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 492 #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 493 #define ERROR_INT_STATUS_WAKEUP_MASK \ 494 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 495 #define ERROR_INT_STATUS_WAKEUP_LSB \ 496 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 497 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 498 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 499 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 500 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 501 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 502 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 503 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 504 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 505 #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 506 #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 507 #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 508 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 509 #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 510 #define HOST_INT_STATUS_COUNTER_MASK \ 511 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 512 #define HOST_INT_STATUS_COUNTER_LSB \ 513 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 514 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 515 #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 516 #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 517 #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 518 #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 519 #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 520 #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 521 #define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 522 #define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 523 #define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 524 #define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 525 #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 526 #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 527 #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 528 #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 529 #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 530 #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 531 532 #define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY) 533 534 #if defined(SDIO_3_0) 535 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 536 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 537 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 538 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 539 #endif 540 541 #if !defined(SOC_PCIE_BASE_ADDRESS) 542 #define SOC_PCIE_BASE_ADDRESS 0 543 #endif 544 545 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 546 #define PCIE_SOC_RDY_STATUS_ADDRESS 0 547 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 548 #endif 549 550 #if !defined(MSI_MAGIC_ADR_ADDRESS) 551 #define MSI_MAGIC_ADR_ADDRESS 0 552 #define MSI_MAGIC_ADDRESS 0 553 #endif 554 555 /* SET/GET macros */ 556 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 557 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 558 #define INT_STATUS_ENABLE_CPU_SET(x) \ 559 (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 560 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 561 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 562 INT_STATUS_ENABLE_COUNTER_MASK) 563 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 564 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 565 INT_STATUS_ENABLE_MBOX_DATA_MASK) 566 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 567 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 568 CPU_INT_STATUS_ENABLE_BIT_MASK) 569 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 570 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 571 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 572 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 573 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 574 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 575 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 576 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 577 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 578 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 579 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 580 ERROR_INT_STATUS_WAKEUP_LSB) 581 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 582 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 583 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 584 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 585 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 586 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 587 #define HOST_INT_STATUS_CPU_GET(x) \ 588 (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 589 #define HOST_INT_STATUS_ERROR_GET(x) \ 590 (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 591 #define HOST_INT_STATUS_COUNTER_GET(x) \ 592 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 593 #define RTC_STATE_V_GET(x) \ 594 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 595 #if defined(SDIO_3_0) 596 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 597 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 598 HOST_INT_STATUS_MBOX_DATA_LSB) 599 #endif 600 601 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 602 603 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 604 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 605 #define AR6320_CPU_SPEED_ADDR 0x403fa4 606 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 607 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 608 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 609 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 610 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 611 #define AR6320V3_CPU_SPEED_ADDR 0x404024 612 613 enum a_refclk_speed_t { 614 SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 615 SOC_REFCLK_48_MHZ = 0, 616 SOC_REFCLK_19_2_MHZ = 1, 617 SOC_REFCLK_24_MHZ = 2, 618 SOC_REFCLK_26_MHZ = 3, 619 SOC_REFCLK_37_4_MHZ = 4, 620 SOC_REFCLK_38_4_MHZ = 5, 621 SOC_REFCLK_40_MHZ = 6, 622 SOC_REFCLK_52_MHZ = 7, 623 }; 624 625 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 626 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 627 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 628 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 629 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 630 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 631 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 632 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 633 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 634 635 #define TARGET_CPU_FREQ 176000000 636 637 struct wlan_pll_s { 638 uint32_t refdiv; 639 uint32_t div; 640 uint32_t rnfrac; 641 uint32_t outdiv; 642 }; 643 644 struct cmnos_clock_s { 645 enum a_refclk_speed_t refclk_speed; 646 uint32_t refclk_hz; 647 uint32_t pll_settling_time; /* 50us */ 648 struct wlan_pll_s wlan_pll; 649 }; 650 651 struct tgt_reg_section { 652 uint32_t start_addr; 653 uint32_t end_addr; 654 }; 655 656 struct tgt_reg_table { 657 const struct tgt_reg_section *section; 658 uint32_t section_size; 659 }; 660 661 struct hif_softc; 662 void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type); 663 void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type); 664 665 #endif /* _REGTABLE_PCIE_H_ */ 666