/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | radeon_object.c | 527 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate() 532 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate() 548 if (!bo->tiling_flags) in radeon_bo_get_surface_reg() 586 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg() 608 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument 616 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags() 617 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags() 618 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags() 619 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags() 620 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags() [all …]
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D | radeon_fbdev.c | 64 u32 tiling_flags = 0; in radeon_fbdev_create_pinned_object() local 91 tiling_flags = RADEON_TILING_MACRO; in radeon_fbdev_create_pinned_object() 96 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeon_fbdev_create_pinned_object() 99 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeon_fbdev_create_pinned_object() 106 if (tiling_flags) { in radeon_fbdev_create_pinned_object() 108 tiling_flags | RADEON_TILING_SURFACE, in radeon_fbdev_create_pinned_object()
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D | r300.c | 718 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 720 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 722 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check() 787 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 789 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 791 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check() 872 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 874 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 876 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
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D | r200.c | 221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check() 223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check() 293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check() 295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
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D | radeon_object.h | 158 u32 tiling_flags, u32 pitch); 160 u32 *tiling_flags, u32 *pitch);
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D | radeon_legacy_crtc.c | 386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local 464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base() 466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base() 483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base() 499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
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D | evergreen_cs.c | 94 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument 96 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode() 98 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode() 1181 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg() 1182 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg() 1183 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg() 1186 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg() 1367 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg() 1368 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg() 1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg() [all …]
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D | atombios_crtc.c | 1145 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local 1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base() 1265 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base() 1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base() 1339 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base() 1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local 1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base() 1577 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base() 1579 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base() 1582 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base() [all …]
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D | r100.c | 1312 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset() 1314 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset() 1654 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check() 1656 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check() 1735 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check() 1737 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check() 3112 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument 3119 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg() 3122 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg() 3125 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg() [all …]
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D | r600_cs.c | 1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg() 1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg() 1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg() 1474 u32 tiling_flags) in r600_check_texture_resource() argument 1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource() 1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource() 1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check() 1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check() 1985 reloc->tiling_flags); in r600_packet3_check()
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D | radeon_gem.c | 568 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl() 589 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
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D | radeon_display.c | 491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local 543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target() 551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
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D | radeon_vm.c | 147 list[0].tiling_flags = 0; in radeon_vm_get_bos() 159 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_display.c | 203 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local 259 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target() 729 int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE); in convert_tiling_flags_to_modifier_gfx12() 735 AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in convert_tiling_flags_to_modifier_gfx12() 760 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier() 763 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier() 772 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier() 858 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier() 865 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier() 890 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier() [all …]
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D | amdgpu_object.h | 130 u64 tiling_flags; member 310 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 311 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
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D | amdgpu_object.c | 1015 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument 1022 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags() 1026 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags() 1038 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument 1046 if (tiling_flags) in amdgpu_bo_get_tiling_flags() 1047 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
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D | dce_v6_0.c | 1836 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local 1873 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base() 1956 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base() 1959 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base() 1960 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base() 1961 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base() 1962 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base() 1963 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base() 1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base() 1975 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
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D | dce_v8_0.c | 1802 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local 1840 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base() 1843 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base() 1925 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base() 1928 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base() 1929 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base() 1930 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base() 1931 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base() 1932 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base() 1941 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
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D | dce_v10_0.c | 1855 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local 1893 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base() 1896 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base() 1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base() 1989 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base() 1990 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base() 1991 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base() 1992 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base() 1993 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base() 2006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
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D | dce_v11_0.c | 1905 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local 1943 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base() 1946 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base() 2036 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base() 2039 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base() 2040 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base() 2041 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base() 2042 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base() 2043 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base() 2056 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
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D | amdgpu_ttm.c | 311 uint64_t from, to, cur_size, tiling_flags; in amdgpu_ttm_copy_mem_to_mem() local 339 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags); in amdgpu_ttm_copy_mem_to_mem() 340 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in amdgpu_ttm_copy_mem_to_mem() 341 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); in amdgpu_ttm_copy_mem_to_mem() 342 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); in amdgpu_ttm_copy_mem_to_mem()
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D | amdgpu_mode.h | 302 uint64_t tiling_flags; member
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/linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm_plane.c | 180 uint64_t tiling_flags) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument 183 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 186 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 187 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 188 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 189 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 190 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 202 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 208 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() 837 const uint64_t tiling_flags, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument [all …]
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D | amdgpu_dm_plane.h | 49 const uint64_t tiling_flags,
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/linux-6.12.1/include/uapi/drm/ |
D | radeon_drm.h | 858 __u32 tiling_flags; member 864 __u32 tiling_flags; member
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