1145 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;  in dce4_crtc_do_set_base()  local
1182 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);  in dce4_crtc_do_set_base()
1265 	if (tiling_flags & RADEON_TILING_MACRO) {  in dce4_crtc_do_set_base()
1266 		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);  in dce4_crtc_do_set_base()
1339 	} else if (tiling_flags & RADEON_TILING_MICRO)  in dce4_crtc_do_set_base()
1466 	uint32_t fb_format, fb_pitch_pixels, tiling_flags;  in avivo_crtc_do_set_base()  local
1501 	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);  in avivo_crtc_do_set_base()
1577 		if (tiling_flags & RADEON_TILING_MACRO)  in avivo_crtc_do_set_base()
1579 		else if (tiling_flags & RADEON_TILING_MICRO)  in avivo_crtc_do_set_base()
1582 		if (tiling_flags & RADEON_TILING_MACRO)  in avivo_crtc_do_set_base()
1585 		if (tiling_flags & RADEON_TILING_MICRO)  in avivo_crtc_do_set_base()