203 	u64 tiling_flags;  in amdgpu_display_crtc_page_flip_target()  local
259 	amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);  in amdgpu_display_crtc_page_flip_target()
729 	int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);  in convert_tiling_flags_to_modifier_gfx12()
735 			AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);  in convert_tiling_flags_to_modifier_gfx12()
760 	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {  in convert_tiling_flags_to_modifier()
763 		int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);  in convert_tiling_flags_to_modifier()
772 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);  in convert_tiling_flags_to_modifier()
858 			   AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |  in convert_tiling_flags_to_modifier()
865 			bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;  in convert_tiling_flags_to_modifier()
890 				AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;  in convert_tiling_flags_to_modifier()
949 	if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */  in check_tiling_flags_gfx6()
952 	micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);  in check_tiling_flags_gfx6()
1163 				      uint64_t *tiling_flags, bool *tmz_surface,  in amdgpu_display_get_fb_info()  argument
1170 		*tiling_flags = 0;  in amdgpu_display_get_fb_info()
1186 	amdgpu_bo_get_tiling_flags(rbo, tiling_flags);  in amdgpu_display_get_fb_info()
1257 	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface,  in amdgpu_display_framebuffer_init()
1279 				    rfb->tiling_flags);  in amdgpu_display_framebuffer_init()