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Searched refs:reg_base (Results 1 – 25 of 422) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-bcm-kona.c61 void __iomem *reg_base; member
76 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
79 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
80 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
92 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
94 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
108 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
110 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
118 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
121 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
Dgpio-amdpt.c28 void __iomem *reg_base; member
41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
49 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
88 pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in pt_gpio_probe()
89 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
91 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
95 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
96 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
[all …]
Dgpio-loongson1.c21 void __iomem *reg_base; member
30 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), in ls1x_gpio_request()
31 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_request()
43 __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), in ls1x_gpio_free()
44 ls1x_gc->reg_base + GPIO_CFG); in ls1x_gpio_free()
58 ls1x_gc->reg_base = devm_platform_ioremap_resource(pdev, 0); in ls1x_gpio_probe()
59 if (IS_ERR(ls1x_gc->reg_base)) in ls1x_gpio_probe()
60 return PTR_ERR(ls1x_gc->reg_base); in ls1x_gpio_probe()
62 ret = bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, in ls1x_gpio_probe()
63 ls1x_gc->reg_base + GPIO_OUTPUT, NULL, in ls1x_gpio_probe()
[all …]
Dgpio-loongson-64bit.c36 void __iomem *reg_base; member
50 writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin); in loongson_commit_direction()
57 writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin); in loongson_commit_level()
91 bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin); in loongson_gpio_get()
102 bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin); in loongson_gpio_get_direction()
127 u = readl(lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4); in loongson_gpio_to_irq()
129 writel(u, lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4); in loongson_gpio_to_irq()
131 writeb(1, lgpio->reg_base + lgpio->chip_data->inten_offset + offset); in loongson_gpio_to_irq()
138 void __iomem *reg_base) in loongson_gpio_init() argument
143 lgpio->reg_base = reg_base; in loongson_gpio_init()
[all …]
/linux-6.12.1/arch/sh/drivers/pci/
Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
105 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
132 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
177 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
/linux-6.12.1/drivers/spi/
Dspi-gxp.c43 void __iomem *reg_base; member
53 void __iomem *reg_base = spifi->reg_base; in gxp_spi_set_mode() local
55 value = readb(reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
58 writeb(0x55, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
59 writeb(0xaa, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
64 writeb(value, reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
71 void __iomem *reg_base = spifi->reg_base; in gxp_spi_read_reg() local
74 value = readl(reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
79 writel(value, reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
81 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_read_reg()
[all …]
Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
243 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
247 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
255 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
260 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
285 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
371 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
389 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
Dspi-cadence-quadspi.c442 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local
446 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
449 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
452 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
469 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local
479 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); in cqspi_setup_opcode_ext()
482 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); in cqspi_setup_opcode_ext()
491 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local
495 reg = readl(reg_base + CQSPI_REG_CONFIG); in cqspi_enable_dtr()
517 writel(reg, reg_base + CQSPI_REG_CONFIG); in cqspi_enable_dtr()
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, in ck_set_gc() argument
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
181 writel(0x0, reg_base + GX_INTC_NMASK31_00); in gx_intc_init()
[all …]
Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/linux-6.12.1/drivers/net/ethernet/cavium/thunder/
Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/linux-6.12.1/drivers/ata/
Dahci_qoriq.c61 struct ccsr_ahci *reg_base; member
167 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
175 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
183 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
193 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
[all …]
/linux-6.12.1/drivers/misc/mchp_pci1xxxx/
Dmchp_pci1xxxx_gpio.c39 void __iomem *reg_base; member
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
[all …]
/linux-6.12.1/drivers/remoteproc/
Dqcom_q6v5_wcss.c110 void __iomem *reg_base; member
162 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
164 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
167 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
169 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
172 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
181 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
183 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
188 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
191 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
[all …]
Dmtk_scp.c175 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
177 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
184 val = readl(scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
186 writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
191 writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); in mt8192_scp_reset_assert()
196 writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR); in mt8192_scp_reset_deassert()
201 writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET); in mt8195_scp_c1_reset_assert()
206 writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR); in mt8195_scp_c1_reset_deassert()
213 scp_to_host = readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
221 scp->cluster->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
[all …]
/linux-6.12.1/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Dptp.c130 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_reset_thresh()
134 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_reset_thresh()
159 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
161 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
174 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec()
258 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_atomic_update()
259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
261 ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_atomic_update()
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
53 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
72 reg_base = devm_platform_ioremap_resource(pdev, 0); in s5pv210_audss_clk_probe()
73 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe()
74 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
127 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
131 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
134 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
Dclk-exynos-audss.c21 static void __iomem *reg_base; variable
46 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
56 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
138 reg_base = devm_platform_ioremap_resource(pdev, 0); in exynos_audss_clk_probe()
139 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
140 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
186 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
197 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
201 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
205 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/linux-6.12.1/drivers/rtc/
Drtc-zynqmp.c52 void __iomem *reg_base; member
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
143 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
[all …]
/linux-6.12.1/arch/arm/mach-rockchip/
Drockchip.c25 void __iomem *reg_base; in rockchip_timer_init() local
32 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
33 if (reg_base) { in rockchip_timer_init()
34 writel(0, reg_base + 0x30); in rockchip_timer_init()
35 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
36 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
37 writel(1, reg_base + 0x30); in rockchip_timer_init()
39 iounmap(reg_base); in rockchip_timer_init()
/linux-6.12.1/drivers/input/serio/
Dsun4i-ps2.c85 void __iomem *reg_base; member
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/linux-6.12.1/arch/powerpc/boot/
Dns16550.c31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
/linux-6.12.1/drivers/fpga/
Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
186 priv->reg_base = reg_base; in alt_pr_register()
[all …]

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