442 	void __iomem *reg_base = cqspi->iobase;  in cqspi_exec_flash_cmd()  local
446 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_exec_flash_cmd()
449 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_exec_flash_cmd()
452 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,  in cqspi_exec_flash_cmd()
469 	void __iomem *reg_base = cqspi->iobase;  in cqspi_setup_opcode_ext()  local
479 	reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);  in cqspi_setup_opcode_ext()
482 	writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);  in cqspi_setup_opcode_ext()
491 	void __iomem *reg_base = cqspi->iobase;  in cqspi_enable_dtr()  local
495 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
517 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
526 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_read()  local
555 	writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_command_read()
578 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_read()
585 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);  in cqspi_command_read()
593 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);  in cqspi_command_read()
600 	writel(0, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_command_read()
609 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_write()  local
630 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_command_write()
645 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_write()
656 		writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);  in cqspi_command_write()
662 			writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);  in cqspi_command_write()
669 	writel(0, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_command_write()
678 	void __iomem *reg_base = cqspi->iobase;  in cqspi_read_setup()  local
706 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_read_setup()
709 	reg = readl(reg_base + CQSPI_REG_SIZE);  in cqspi_read_setup()
712 	writel(reg, reg_base + CQSPI_REG_SIZE);  in cqspi_read_setup()
723 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_read_execute()  local
731 	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);  in cqspi_indirect_read_execute()
732 	writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);  in cqspi_indirect_read_execute()
735 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_indirect_read_execute()
746 		writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
748 		writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
750 		writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
754 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
767 			writel(0x0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
803 				writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
808 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,  in cqspi_indirect_read_execute()
816 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
819 	writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
825 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
829 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
835 	void __iomem *reg_base = cqspi->iobase;  in cqspi_controller_enable()  local
838 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
845 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
854 	void __iomem *reg_base = cqspi->iobase;  in cqspi_versal_indirect_read_dma()  local
886 	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);  in cqspi_versal_indirect_read_dma()
887 	writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);  in cqspi_versal_indirect_read_dma()
889 	       reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);  in cqspi_versal_indirect_read_dma()
892 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_versal_indirect_read_dma()
896 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);  in cqspi_versal_indirect_read_dma()
899 	writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);  in cqspi_versal_indirect_read_dma()
903 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);  in cqspi_versal_indirect_read_dma()
905 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);  in cqspi_versal_indirect_read_dma()
908 	writel(cqspi->trigger_address, reg_base +  in cqspi_versal_indirect_read_dma()
912 	writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);  in cqspi_versal_indirect_read_dma()
916 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);  in cqspi_versal_indirect_read_dma()
919 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_versal_indirect_read_dma()
964 	writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);  in cqspi_versal_indirect_read_dma()
968 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_versal_indirect_read_dma()
987 	void __iomem *reg_base = cqspi->iobase;  in cqspi_write_setup()  local
1003 	writel(reg, reg_base + CQSPI_REG_WR_INSTR);  in cqspi_write_setup()
1005 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_write_setup()
1019 		reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);  in cqspi_write_setup()
1021 		writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);  in cqspi_write_setup()
1030 	reg = readl(reg_base + CQSPI_REG_SIZE);  in cqspi_write_setup()
1033 	writel(reg, reg_base + CQSPI_REG_SIZE);  in cqspi_write_setup()
1043 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_write_execute()  local
1048 	writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);  in cqspi_indirect_write_execute()
1049 	writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);  in cqspi_indirect_write_execute()
1052 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_indirect_write_execute()
1054 	writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1058 	       reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1074 		readl(reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1109 	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,  in cqspi_indirect_write_execute()
1117 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1120 	writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1128 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1132 	       reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1139 	void __iomem *reg_base = cqspi->iobase;  in cqspi_chipselect()  local
1143 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1162 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1211 	void __iomem *reg_base = cqspi->iobase;  in cqspi_config_baudrate_div()  local
1225 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1228 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1235 	void __iomem *reg_base = cqspi->iobase;  in cqspi_readdata_capture()  local
1238 	reg = readl(reg_base + CQSPI_REG_READCAPTURE);  in cqspi_readdata_capture()
1251 	writel(reg, reg_base + CQSPI_REG_READCAPTURE);  in cqspi_readdata_capture()