Lines Matching refs:reg_base
39 void __iomem *reg_base; member
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
124 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val); in pci1xxxx_gpio_set()
138 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
141 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
144 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
145 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false); in pci1xxxx_gpio_set_config()
148 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true); in pci1xxxx_gpio_set_config()
167 pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true); in pci1xxxx_gpio_irq_ack()
181 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); in pci1xxxx_gpio_irq_set_mask()
205 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
207 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), in pci1xxxx_gpio_set_type()
211 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
216 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
218 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
222 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio), in pci1xxxx_gpio_set_type()
227 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
229 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
231 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
237 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio), in pci1xxxx_gpio_set_type()
239 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), in pci1xxxx_gpio_set_type()
241 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos, in pci1xxxx_gpio_set_type()
247 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true); in pci1xxxx_gpio_set_type()
263 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true); in pci1xxxx_gpio_irq_handler()
267 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
277 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank)); in pci1xxxx_gpio_irq_handler()
284 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false); in pci1xxxx_gpio_irq_handler()
306 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
308 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_suspend()
310 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true); in pci1xxxx_gpio_suspend()
322 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
324 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, in pci1xxxx_gpio_resume()
326 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false); in pci1xxxx_gpio_resume()
397 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800); in pci1xxxx_gpio_probe()
398 if (!priv->reg_base) in pci1xxxx_gpio_probe()
401 writel(0x0264, (priv->reg_base + 0x400 + 0xF0)); in pci1xxxx_gpio_probe()