Home
last modified time | relevance | path

Searched refs:io_base (Results 1 – 25 of 173) sorted by relevance

1234567

/linux-6.12.1/drivers/staging/vt6655/
Dmac.c100 void __iomem *io_base = priv->port_offset; in vt6655_mac_is_reg_bits_off() local
102 return !(ioread8(io_base + reg_offset) & mask); in vt6655_mac_is_reg_bits_off()
121 void __iomem *io_base = priv->port_offset; in vt6655_mac_set_short_retry_limit() local
123 iowrite8(retry_limit, io_base + MAC_REG_SRT); in vt6655_mac_set_short_retry_limit()
143 void __iomem *io_base = priv->port_offset; in MACvSetLongRetryLimit() local
145 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); in MACvSetLongRetryLimit()
164 void __iomem *io_base = priv->port_offset; in vt6655_mac_set_loopback_mode() local
168 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | loopback_mode, io_base + MAC_REG_TEST); in vt6655_mac_set_loopback_mode()
186 void __iomem *io_base = priv->port_offset; in vt6655_mac_save_context() local
189 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0); in vt6655_mac_save_context()
[all …]
/linux-6.12.1/drivers/gpu/drm/meson/
Dmeson_venc.c1046 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1057 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1060 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1071 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1073 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_viu.c86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_crtc.c100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
[all …]
Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
/linux-6.12.1/arch/powerpc/platforms/embedded6xx/
Dflipper-pic.c49 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask_and_ack() local
52 clrbits32(io_base + FLIPPER_IMR, mask); in flipper_pic_mask_and_ack()
54 out_be32(io_base + FLIPPER_ICR, mask); in flipper_pic_mask_and_ack()
60 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_ack() local
63 out_be32(io_base + FLIPPER_ICR, 1 << irq); in flipper_pic_ack()
69 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask() local
71 clrbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_mask()
77 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_unmask() local
79 setbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_unmask()
116 static void __flipper_quiesce(void __iomem *io_base) in __flipper_quiesce() argument
[all …]
Dhlwd-pic.c45 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask_and_ack() local
48 clrbits32(io_base + HW_BROADWAY_IMR, mask); in hlwd_pic_mask_and_ack()
49 out_be32(io_base + HW_BROADWAY_ICR, mask); in hlwd_pic_mask_and_ack()
55 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_ack() local
57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); in hlwd_pic_ack()
63 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask() local
65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_mask()
71 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_unmask() local
73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_unmask()
76 clrbits32(io_base + HW_STARLET_IMR, 1 << irq); in hlwd_pic_unmask()
[all …]
/linux-6.12.1/sound/isa/
Dsscape.c133 unsigned io_base; member
189 static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg, in sscape_write_unsafe() argument
192 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_write_unsafe()
193 outb(val, ODIE_DATA_IO(io_base)); in sscape_write_unsafe()
206 sscape_write_unsafe(s->io_base, reg, val); in sscape_write()
214 static inline unsigned char sscape_read_unsafe(unsigned io_base, in sscape_read_unsafe() argument
217 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_read_unsafe()
218 return inb(ODIE_DATA_IO(io_base)); in sscape_read_unsafe()
224 static inline void set_host_mode_unsafe(unsigned io_base) in set_host_mode_unsafe() argument
226 outb(0x0, HOST_CTRL_IO(io_base)); in set_host_mode_unsafe()
[all …]
/linux-6.12.1/drivers/watchdog/
Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
[all …]
Dnic7018_wdt.c46 u16 io_base; member
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
126 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
128 outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_stop()
[all …]
/linux-6.12.1/sound/soc/spear/
Dspdif_in.c38 void *io_base; member
52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_configure()
53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_configure()
74 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_shutdown()
79 u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
131 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_trigger()
137 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
[all …]
Dspdif_out.c39 void __iomem *io_base; member
46 writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
48 writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET, in spdif_out_configure()
49 host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
54 host->io_base + SPDIF_OUT_CFG); in spdif_out_configure()
56 writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR); in spdif_out_configure()
57 writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR); in spdif_out_configure()
99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
165 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_trigger()
[all …]
/linux-6.12.1/drivers/fpga/
Dts73xx-fpga.c31 void __iomem *io_base; member
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
59 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, in ts73xx_fpga_write()
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
[all …]
/linux-6.12.1/drivers/crypto/hisilicon/sec2/
Dsec_main.c433 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
441 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
449 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
452 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
455 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
459 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
462 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
465 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
467 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
474 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
[all …]
/linux-6.12.1/drivers/crypto/hisilicon/hpre/
Dhpre_main.c466 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
467 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
475 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
476 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
519 qm->io_base + offset + HPRE_CORE_ENB); in hpre_set_cluster()
520 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); in hpre_set_cluster()
521 ret = readl_relaxed_poll_timeout(qm->io_base + offset + in hpre_set_cluster()
546 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
549 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
550 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in disable_flr_of_bme()
[all …]
/linux-6.12.1/drivers/crypto/intel/keembay/
Docs-hcu.c173 return readl_poll_timeout(hcu_dev->io_base + OCS_HCU_STATUS, val, in ocs_hcu_wait_busy()
182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_done_irq_en()
186 hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_done_irq_en()
192 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR); in ocs_hcu_dma_irq_en()
196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_dma_irq_en()
198 writel(HCU_DMA_MSI_UNMASK, hcu_dev->io_base + OCS_HCU_DMA_MSI_MASK); in ocs_hcu_dma_irq_en()
203 writel(HCU_IRQ_DISABLE, hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_irq_dis()
204 writel(HCU_DMA_MSI_DISABLE, hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_irq_dis()
270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_intermediate_data()
272 data->msg_len_lo = readl(hcu_dev->io_base + OCS_HCU_MSG_LEN_LO); in ocs_hcu_get_intermediate_data()
[all …]
/linux-6.12.1/drivers/hwspinlock/
Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/linux-6.12.1/drivers/mtd/spi-nor/controllers/
Dnxp-spifi.c56 void __iomem *io_base; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
114 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); in nxp_spifi_set_memory_mode_on()
115 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_set_memory_mode_on()
140 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
143 *buf++ = readb(spifi->io_base + SPIFI_DATA); in nxp_spifi_read_reg()
164 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
167 writeb(*buf++, spifi->io_base + SPIFI_DATA); in nxp_spifi_write_reg()
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_ttm_stolen_mgr.c33 resource_size_t io_base; member
81 mgr->io_base = tile->mem.vram.io_start + mgr->stolen_base; in detect_bar2_dgfx()
139 mgr->io_base = pci_resource_start(pdev, 2) + mgr->stolen_base; in detect_bar2_integrated()
173 if (gscpsmi_base >= mgr->io_base && in detect_bar2_integrated()
174 gscpsmi_base < mgr->io_base + stolen_size) { in detect_bar2_integrated()
177 mgr->io_base + stolen_size - gscpsmi_base); in detect_bar2_integrated()
178 stolen_size = gscpsmi_base - mgr->io_base; in detect_bar2_integrated()
194 mgr->io_base = pci_resource_start(to_pci_dev(xe->drm.dev), 2); in detect_stolen()
236 if (mgr->io_base && !xe_ttm_stolen_cpu_access_needs_ggtt(xe)) in xe_ttm_stolen_mgr_init()
250 mgr->mapping = devm_ioremap_wc(&pdev->dev, mgr->io_base, io_size); in xe_ttm_stolen_mgr_init()
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
Dlpc32xx_slc.c219 void __iomem *io_base; member
241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
245 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
246 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
248 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
264 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
277 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
282 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
286 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
/linux-6.12.1/drivers/mtd/devices/
Dspear_smi.c174 void __iomem *io_base; member
229 ctrlreg1 = readl(dev->io_base + SMI_CR1); in spear_smi_read_sr()
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
301 status = readl(dev->io_base + SMI_SR); in spear_smi_int_handler()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
[all …]
/linux-6.12.1/drivers/input/keyboard/
Dspear-keyboard.c57 void __iomem *io_base; member
76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
140 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
[all …]
/linux-6.12.1/drivers/crypto/hisilicon/zip/
Dzip_main.c457 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
464 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
465 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
483 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
485 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
487 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, in hisi_zip_open_sva_prefetch()
502 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
504 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
506 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
520 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
[all …]
/linux-6.12.1/drivers/spi/
Dspi-stm32-qspi.c104 void __iomem *io_base; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
192 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
[all …]

1234567