466 	val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG);  in hpre_config_pasid()
467 	val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG);  in hpre_config_pasid()
475 	writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);  in hpre_config_pasid()
476 	writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);  in hpre_config_pasid()
519 		       qm->io_base + offset + HPRE_CORE_ENB);  in hpre_set_cluster()
520 		writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);  in hpre_set_cluster()
521 		ret = readl_relaxed_poll_timeout(qm->io_base + offset +  in hpre_set_cluster()
546 	val = readl(qm->io_base + QM_PEH_AXUSER_CFG);  in disable_flr_of_bme()
549 	writel(val, qm->io_base + QM_PEH_AXUSER_CFG);  in disable_flr_of_bme()
550 	writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);  in disable_flr_of_bme()
562 	val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);  in hpre_open_sva_prefetch()
564 	writel(val, qm->io_base + HPRE_PREFETCH_CFG);  in hpre_open_sva_prefetch()
566 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,  in hpre_open_sva_prefetch()
582 	val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);  in hpre_close_sva_prefetch()
584 	writel(val, qm->io_base + HPRE_PREFETCH_CFG);  in hpre_close_sva_prefetch()
586 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,  in hpre_close_sva_prefetch()
601 	val = readl(qm->io_base + HPRE_CLKGATE_CTL);  in hpre_enable_clock_gate()
603 	writel(val, qm->io_base + HPRE_CLKGATE_CTL);  in hpre_enable_clock_gate()
605 	val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);  in hpre_enable_clock_gate()
607 	writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);  in hpre_enable_clock_gate()
609 	val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);  in hpre_enable_clock_gate()
611 	writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);  in hpre_enable_clock_gate()
613 	val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);  in hpre_enable_clock_gate()
615 	writel(val, qm->io_base + HPRE_CORE_SHB_CFG);  in hpre_enable_clock_gate()
625 	val = readl(qm->io_base + HPRE_CLKGATE_CTL);  in hpre_disable_clock_gate()
627 	writel(val, qm->io_base + HPRE_CLKGATE_CTL);  in hpre_disable_clock_gate()
629 	val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);  in hpre_disable_clock_gate()
631 	writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);  in hpre_disable_clock_gate()
633 	val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);  in hpre_disable_clock_gate()
635 	writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);  in hpre_disable_clock_gate()
637 	val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);  in hpre_disable_clock_gate()
639 	writel(val, qm->io_base + HPRE_CORE_SHB_CFG);  in hpre_disable_clock_gate()
651 	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);  in hpre_set_user_domain_and_cache()
652 	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);  in hpre_set_user_domain_and_cache()
653 	writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);  in hpre_set_user_domain_and_cache()
657 			qm->io_base + HPRE_TYPES_ENB);  in hpre_set_user_domain_and_cache()
659 		writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);  in hpre_set_user_domain_and_cache()
661 	writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);  in hpre_set_user_domain_and_cache()
662 	writel(0x0, qm->io_base + HPRE_BD_ENDIAN);  in hpre_set_user_domain_and_cache()
663 	writel(0x0, qm->io_base + HPRE_POISON_BYPASS);  in hpre_set_user_domain_and_cache()
664 	writel(0x0, qm->io_base + HPRE_ECC_BYPASS);  in hpre_set_user_domain_and_cache()
666 	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);  in hpre_set_user_domain_and_cache()
667 	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);  in hpre_set_user_domain_and_cache()
668 	writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);  in hpre_set_user_domain_and_cache()
669 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,  in hpre_set_user_domain_and_cache()
709 		writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);  in hpre_cnt_regs_clear()
713 	writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);  in hpre_cnt_regs_clear()
722 	val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);  in hpre_master_ooo_ctrl()
733 		writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);  in hpre_master_ooo_ctrl()
735 	writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);  in hpre_master_ooo_ctrl()
746 	writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK);  in hpre_hw_error_disable()
759 	writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT);  in hpre_hw_error_enable()
762 	writel(ce, qm->io_base + HPRE_RAS_CE_ENB);  in hpre_hw_error_enable()
763 	writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);  in hpre_hw_error_enable()
764 	writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);  in hpre_hw_error_enable()
771 	writel(~err_en, qm->io_base + HPRE_INT_MASK);  in hpre_hw_error_enable()
785 	return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &  in hpre_clear_enable_read()
797 	tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &  in hpre_clear_enable_write()
799 	writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);  in hpre_clear_enable_write()
811 	return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);  in hpre_cluster_inqry_read()
821 	writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);  in hpre_cluster_inqry_write()
983 	regset->base = qm->io_base;  in hpre_pf_comm_regs_debugfs_init()
1014 		regset->base = qm->io_base + hpre_cluster_offsets[i];  in hpre_cluster_debugfs_init()
1190 	void __iomem *io_base;  in hpre_show_last_regs_init()  local
1201 		debug->last_words[i] = readl_relaxed(qm->io_base +  in hpre_show_last_regs_init()
1205 		io_base = qm->io_base + hpre_cluster_offsets[i];  in hpre_show_last_regs_init()
1209 				io_base + hpre_cluster_dfx_regs[j].offset);  in hpre_show_last_regs_init()
1233 	void __iomem *io_base;  in hpre_show_last_dfx_regs()  local
1243 		val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);  in hpre_show_last_dfx_regs()
1251 		io_base = qm->io_base + hpre_cluster_offsets[i];  in hpre_show_last_dfx_regs()
1253 			val = readl_relaxed(io_base +  in hpre_show_last_dfx_regs()
1278 	return readl(qm->io_base + HPRE_INT_STATUS);  in hpre_get_hw_err_status()
1285 	writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);  in hpre_clear_hw_err_status()
1287 	writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);  in hpre_clear_hw_err_status()
1294 	value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);  in hpre_open_axi_master_ooo()
1296 	       qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);  in hpre_open_axi_master_ooo()
1298 	       qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);  in hpre_open_axi_master_ooo()